VC Verification IP for DDR2

Synopsys® VC Verification IP for DDR2 provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of DDR2 designs.

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Verification IP for DDR2


  • Native SystemVerilog/UVM testbench
  • Memory model certification
  • Runs natively on all major simulators
  • Runtime JEDEC and vendor part selection
  • Built-in protocol and timing checks
  • Overriding timing parameters
  • Bypass initialization
  • Backdoor memory access
  • Error injection & timing exceptions
  • Trace files and debug ports
  • Delay modeling: Fly by Delay, Trace Delays, Pre and Post buffer delays

Key Features

  • JEDEC JESD79-2E DDR2 SDRAM device standard
  • Write burst interrupt
  • Override logical address formatting as per application level address of host
  • Includes DFI monitor