About PCI Express

Synopsys Verification IP (VIP) for PCIe provides verification of design implementations based on all PCIe specifications (PCIe 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0) which can be used in SoCs and System Level Desings to accelerate verification closure. Synopsys VIP provides support for various Interfaces- Serial, PIPE, PIE8, and SerDes. Synopsys PCIe VIP provides verification for Root Complex and End Point device configurations.

Key Benefits

Native Integration Icon | Synopsys VIP for CXL

Native SystemVerilog/UVM

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Source Code Test Suits Available

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Built-in Protocol Checks

Chip Icon | Synopsys VIP for CXL

Complete Subsystem Verification Solution

Verification IP for PCIe


  • Native System Verilog/UVM
  • Source code test suite (optional)
  • Runs on all major simulators
  • Built-in protocol checks
  • Verdi protocol-aware debug
  • Verification plan and coverage



Specification Version

PCIe 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0

Device Configuration

Root Complex, Endpoint


Serial (NRZ, PAM-4), Original PIPE, PIE8, SerDes

Link Rate

2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32.0GT/s, 64.0GT/s

Link Width

x1, x2, x4, x8, x12, x16, x32

PIPE Support

· Specification Version- 2.0, 4.0, 4.2, 4.3, 4.4, 5.1, 5.2, 6.0

· PIPE Width- 8/10 bits, 16/20 bits, 32/40 bits, 64/80 bits

· RxStandby/RxStandbyStatus Handshake Support (PIPE5.1 or later)

· Nominal Empty Mode for EFIFO (Elastic Buffer Mode) Support (PIPE 4.4 or later)

· RxValid synchronous to RxCLK in SerDes mode

· Loopback updates including equalization bypass (for lanes under test)

Protocol Support

· Version- CCIX Transport, Release 2 Draft specification, March 2017

· Interface- Serial and PIPE 4.4


PCIe TLMs at TL/DL, PIPE SerDes Architecture, Serial

Side-Band Signal Support


Retimer Support

Root Complex and End Point support for recognizing retimer in the topology

FLIT support

· FLIT support for Gen6 and beyond

· CRC detection in FLITS

· FLIT mode TLP header, DLLP, NOP, NOP2

· 8b/10b FLIT mode

· 128b/130 bit FLIT mode


Protocol Timers

Full configuration capability, ACK, NAK, Replay timer simplification for Gen 4.0

Fault Isolation

Advanced error reporting (AER) to assist in fault isolation and root cause analysis

Transaction Layer

Tag Scaling, Interrupts (MSI, MSI-X, INTx)

Data Link Layer

Virtual Channel, Flow Control Credit (FCC), Ack\Nak

Physical Layer

· Equalization procedure support, error injection, and checks

· RX Margining, Clock Compensation

· Nominal Empty Elastic Buffer mode, Nominal Half Full Elastic Buffer mode

· Electrical Idle, LTSSM, Skew

· Full support for up and down configuration

· Injecting and checking framing tokens errors

· DC Balance checks and coverage

· Multi-Lane RX Error reporting per lane in the Lane Error Status register

· Precoding support, Polling Compliance, Gray coding

Clock Recovery

Clock recovery mechanisms supported: Incoming bit stream, Reference clock

Clock Jitter

Ability to add jitter to clock

Address Space

Support for all types of address spaces: Memory, I/O, MSI and MSI-X

Function Level Reset (FLR)

Full compliance

Power Management

Full power management support: D-states, L-States, ASPM




Alternate routine ID (ARI)

ECN Support

· Process Address Space ID (PASID), PASID Translation

·  lternative Routing-ID Interpretation (ARI)

·  Atomic Operations, ID-Based Ordering

· Latency Tolerance Reporting (LTR)

· Extended Tag Enable Default

· Data Object Exchange (DOE)

· TLP Processing Hints, TLP Prefix, End-End TLP Prefix Changes for RC

· Optimized Buffer Flush/FiIll (OBFF), ASPM Option

· Separate Refclk Independent SSC Architecture (SRIS)

· Precision Time Measurement (PTM) Revision 1.0

· L1 PM sub-state with CLKREQ

· Deferred Memory Write (DMWr) ECN

· Integrity and Data Encryption (IDE) ECR


Protocol Analyzer, Scoreboard, Protocol Checks at each level, Functional Coverage


Support all Major Simulators


Native SystemVerilog/UVM

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