Verification IP for DDR5

Synopsys® Verification IP for JEDEC DDR5 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DDR5/4/3/2 based designs.

This VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. It is natively integrated with Verdi® Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottlenecks.

The availability of Synopsys' design-proven DDR5 VIP delivers a new level of confidence to end customers by enabling verification closure of industry-first JEDEC 1.0 DDR5 devices."

Malcolm Humphrey


Vice President of Marketing, Micron

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.


  • Native SystemVerilog/UVM/OVM
  • Memory model certification
  • Access to vendor specifications and memory models
  • Runs natively on all major simulators
  • All JEDEC parts
  • Runtime JEDEC and vendor part selection
  • Verification plan and coverage
  • Built-in protocol and timing checks
  • Verdi Protocol and Memory Analyzer
  • Dynamic reconfiguration
  • Backdoor memory/mode registers access
  • Bypass/fast initialization
  • Error injection & exceptions
  • Trace file and debug ports for easy debug
  • Delay modeling: fly by delay, trace delay, buffer delays
  • DIMM and DRAM level monitors
Verification IP for DDR5


DDR5 DRAM and 3DS  JEDEC rev 1.90


RDIMM (RCD03 rev 1.0)

LRDIMM (DB01 rev 1.0)

All speed bins

All densities (8Gb to 32Gb)

All DRAM data widths (4, 8, 16)

All commands, and burst sizes (BC8/BL32 and on the fly BL)

Sequential and wrap addressing

SDR/DDR modes

Clock stop/frequency change

PDA, MPSM and 2N mode

CA parity and ECC

Trainings (CS, CA, read training pattern, read preamble training, write leveling)

All mode registers

On die termination (ODT)


Partial write, write pattern

Refresh schedule monitoring, configurable refresh rates, refresh management (RFM)

DQS interval oscillator

DRAM + -

RESET and Initialization Procedure

Skip and fast initialization to speed up simulation

All commands

  • MRW, MRR, MPC, RD, WR, ACTIVE, Precharge,
  • PDE, PDX, SRE, SRX, ZQ calibration and other commands

All mode registers

  • WL/RL
  • Preamble/Postamble and other fields

Decision feedback equalization, and loopback

CRC, On-die ECC, DQS Interval oscillator


  • CS, CA, read training pattern, read preamble training, write leveling
  • RCD, DCA and DCS, CA Vref, DQ Vref (2D)

Up to 2 rank, dual channel

DDR and SDR modes

Parity, power down, self refresh, and all DRAM commands

RCD registers, and BCOM bus

Output inversion and mirroring, transparent mode

Callbacks for error generation and commands tracking

Access to internal states of the model

Static/dynamic reconfiguration for timing and configuration settings

Clock jitter (partial)

2D Vref DQ modeling to mimic real world eye

User configurable logical addressing

Pre buffer and post buffer modeling to enable real world trainings

Tested against vendor models

Built-in protocol and timing checks

Functional coverage model and verification plan

Analysis port for score-boarding

Synopsys Verdi Protocol Analyzer and Performance Analyzer

JEDEC and Vendor Part Numbers

Synopsys VIP supports generic JEDEC part numbers with densities ranging from 8Gb to 32Gb, data rates up to 8800 Mbps, and bus width from X4 to X16. It supports core timings according to specific frequencies and densities. Synopsys collaborates with leading memory vendors, including Samsung, SK Hynix, Micron, and Nanya for support of specific vendor part numbers, as they are made available. It also provides a configuration to model all possible JEDEC part numbers virtually. The virtual part number feature enhances productivity, as user need not to request and wait for delivery of the required part number from Synopsys.

Contact the VIP Team