Cloud native EDA tools & pre-optimized hardware platforms
Analog &
Mixed-Signal Design
The Synopsys Custom Design Family is a unified suite of design and verification tools that accelerates the development of robust analog and mixed-signal designs. The family features Custom Compiler™, a fast, easy-to-use design and layout solution, PrimeSim™ solution which delivers industry-leading circuit simulation performance, and best-in-class technologies for parasitic extraction, reliability analysis, and physical verification.
Analog circuits are the foundation of all electronics and analog circuit design requires a multitude of tools for accurate simulation and analysis of these circuits. Synopsys Custom Compiler is a powerful solution for custom analog and mixed-signal schematic and layout design. It is built on the industry leading custom infrastructure which allows a rich set of functionality and a base to integrate any Synopsys or 3rd party tool. Combined with the PrimeWave Design Environment, designers have an open and flexible simulation setup, waveform viewing and post-processing solution, providing full-cycle design and reliability analysis for analog, RF and mm-wave designs. PrimeSim offers a full suite of small-signal and large-signal analog and RF simulation capabilities as well as ML-based High-Sigma Monte Carlo analysis.
Analog design has always been a unique challenge because the inputs and outputs are continuous, rather than discrete, and it requires careful optimization of parameters from a vast design space to converge on a subset of design specifications. With the advances in semiconductor technology to finfets and nanosheets, the impact of process variations and parasitic effects as well as reliability issues such as aging and electro-migration have become much more significant. Whether it is enhanced parasitic handling or device reliability issues for advanced nodes; thermal analysis, power efficiency or semiconductor process exploration for power devices; AI-based design migration and optimization; or advanced variation analysis for memory characterization, the Synopsys Custom Family offers innovative ways to deal with all of these challenges.
The exponential growth in digital data demands an increased need to send more data faster. The latest semiconductor technologies are enabling circuits to perform at faster speeds with lower power consumption. As an example, high speed SerDes (Serializer-Deserializer) circuits enables chip-to-chip communication over a serial link. These incredibly complex circuits include various analog circuits such as bandgaps and regulators but also include high-speed data converters, phase locked loops and wideband amplifiers, all of which require different design and verification techniques. Synopsys is a premier provider of SerDes PHYs and most major SerDes IP providers use Synopsys as their trusted provider of custom and AMS tools.
Integrated silicon photonics technology represents a growing opportunity for designing and manufacturing photonic integrated circuits (PICs) for applications in high-speed data communications, advanced sensing, and imaging. Integrated photonic technologies promise orders-of-magnitude speed improvements with reduced power consumption for data transmission and ultra-sensitive sensing capabilities in multiple domains. Synopsys is accelerating the adoption of photonic IC technologies with a unified electronic and photonic design solution to help IC designers and photonic engineers innovate consumer, health, and industrial applications. Our PIC design automation tools include Synopsys OptoCompiler, Synopsys OptSim, and Synopsys Photonic Device Compiler.
Today’s RFICs are complex chips by themselves and hyperconvergence is combining RF, analog, and digital logic into single devices. With Synopsys Custom Design Family of products, engineers are able to achieve a full design and verification flow for state-of-the-art RF and mm-wave designs. The Synopsys Custom Design Family of products provides support of advanced semiconductor technology node PDKs, including FinFET 16nm~3nm nodes, SOI (Silicon on Insulator), and SiGe (Silicon Germanium) technology nodes, as well as the ability to handle multi-technology designs. The Harmonic Balance and Shooting Newton analyses in PrimeSim provide an efficient solution for simulating RF LNAs, PAs, Mixers, LOs, and for analyzing nonlinear mixer noise and oscillator phase noise.
Recognizing Synopsys with six 2022 TSMC OIP Partner of the Year awards highlights our appreciation for the deep impact our collaboration continues to have on advanced semiconductor design"
Dan Kochpatcharin
|Head of Design Infrastructure Management Division at TSMC
Our long history of collaboration with Synopsys continues to benefit mutual customers who are migrating existing analog designs to next-generation TSMC processes, with productive and time to market gains"
Dan Kochpatcharin,
|Head of Design Infrastructure Management Division at TSMC
We are pleased that the 8nm RF design reference flow and design solution kit that we developed in close collaboration with Ansys and Synopsys will support our mutual customers in meeting the demands of growing design complexity in today's hyper-connected world"
Sangyun Kim
|corporate vice president of the Foundry Design Technology Team at Samsung Electronics
Synopsys gave us a superior solution for advanced node custom design, which helped us meet aggressive power, performance and area targets for our high-speed connectivity IP."
Tony Pialis
|Alphawave founder and CEO
The Analog Circuit Check technology of PrimeSim Reliability Analysis solution accelerated the reliability signoff on our analog IPs by enabling detection of critical design issues early in the design cycle"
Vivek Bhan
|senior vice president, Custom Mixed Signal Business Group at Renesas
The mmWave design reference flow that Synopsys, Ansys and Keysight have developed for TSMC's 16FFC process benefits from its superior performance and power consumption advantage for a tightly integrated solution that enhances productivity and quality-of-results for 5G/6G SoCs."
Dan Kochpatcharin
|Head of Design Infrastructure Management Division at TSMC
The full-custom flow we are deploying, based on the Synopsys Custom Design Platform integrated with Keysight RFPro, provides our designers with an accelerated predictive process for creating high-quality full-custom RF, analog and mixed-signal ICs."
Tomi-Pekka Takalo
|CEO at CoreHW
Recognizing Synopsys with six 2022 TSMC OIP Partner of the Year awards highlights our appreciation for the deep impact our collaboration continues to have on advanced semiconductor design"
Dan Kochpatcharin
|Head of Design Infrastructure Management Division at TSMC
Our long history of collaboration with Synopsys continues to benefit mutual customers who are migrating existing analog designs to next-generation TSMC processes, with productive and time to market gains"
Dan Kochpatcharin,
|Head of Design Infrastructure Management Division at TSMC
We are pleased that the 8nm RF design reference flow and design solution kit that we developed in close collaboration with Ansys and Synopsys will support our mutual customers in meeting the demands of growing design complexity in today's hyper-connected world"
Sangyun Kim
|corporate vice president of the Foundry Design Technology Team at Samsung Electronics
Synopsys gave us a superior solution for advanced node custom design, which helped us meet aggressive power, performance and area targets for our high-speed connectivity IP."
Tony Pialis
|Alphawave founder and CEO
The Analog Circuit Check technology of PrimeSim Reliability Analysis solution accelerated the reliability signoff on our analog IPs by enabling detection of critical design issues early in the design cycle"
Vivek Bhan
|senior vice president, Custom Mixed Signal Business Group at Renesas
The mmWave design reference flow that Synopsys, Ansys and Keysight have developed for TSMC's 16FFC process benefits from its superior performance and power consumption advantage for a tightly integrated solution that enhances productivity and quality-of-results for 5G/6G SoCs."
Dan Kochpatcharin
|Head of Design Infrastructure Management Division at TSMC
The full-custom flow we are deploying, based on the Synopsys Custom Design Platform integrated with Keysight RFPro, provides our designers with an accelerated predictive process for creating high-quality full-custom RF, analog and mixed-signal ICs."
Tomi-Pekka Takalo
|CEO at CoreHW
Recognizing Synopsys with six 2022 TSMC OIP Partner of the Year awards highlights our appreciation for the deep impact our collaboration continues to have on advanced semiconductor design"
Dan Kochpatcharin
|Head of Design Infrastructure Management Division at TSMC
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See the effect of layout while the layout is still in progress.
Now it is the perfect time to take PCells’ power to another level.
On their own, better tools aren’t enough to keep pace with analog design challenges.
Analog designs are challenging, but artificial-intelligence optimizations are improving and speeding up the design process.
The Synopsys SIPI SIG Event 2024 is for signal and power integrity engineers to hear the latest advances and solutions in signal and power integrity from customers and partners.
Rapidly migrate and optimize analog designs in their target technology node.
Attend this 3-part webinar series to learn about the challenges posed on the transmitter and a discussion on techniques used to overcome the challenges of data transmission at 100s of Gbps.
Using AI-driven automation to quickly reimplement analog designs in a new technology node
Design tradeoffs in the choice of multiplexer architecture, equalizer design, serialization technique, and output driver.
See the effect of layout while the layout is still in progress.
Now it is the perfect time to take PCells’ power to another level.
On their own, better tools aren’t enough to keep pace with analog design challenges.
Analog designs are challenging, but artificial-intelligence optimizations are improving and speeding up the design process.
The Synopsys SIPI SIG Event 2024 is for signal and power integrity engineers to hear the latest advances and solutions in signal and power integrity from customers and partners.
Rapidly migrate and optimize analog designs in their target technology node.
Attend this 3-part webinar series to learn about the challenges posed on the transmitter and a discussion on techniques used to overcome the challenges of data transmission at 100s of Gbps.
Using AI-driven automation to quickly reimplement analog designs in a new technology node
Design tradeoffs in the choice of multiplexer architecture, equalizer design, serialization technique, and output driver.
See the effect of layout while the layout is still in progress.
Now it is the perfect time to take PCells’ power to another level.
On their own, better tools aren’t enough to keep pace with analog design challenges.
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