Static & Formal Verification

Synopsys' VC Formal™, VC LP™, VC SpyGlass™, SpyGlass® and Timing Constraints Manager tools enable designers and verification engineers to quickly analyze and check RTL designs very early in the design flow, with no need for complex setup, testbenches or stimulus. This allows many bugs to be found and fixed before simulation, making simulation faster and more effective, and reducing overall cost, time and effort. 

Synopsys VC SpyGlass and VC Formal solutions are built on next-generation databases and engines to provide the capacity and performance required to verify the largest, most complex designs. In addition, VC Formal, VC SpyGlass and VC LP provide unified design read and common look-and-feel with Synopsys Design Compiler-like Tcl support, enabling rapid and easy adoption and excellent ease-of-use and debug. 

Timing Constraints Manager offers an accurate and scalable timing constraints signoff solution with SDC generation, verification using formal, and management for improved PPA and shorter overall TAT.  

Synopsys offers comprehensive CoStart and consulting services to accelerate adoption of these technologies as well as access to experts to help drive these technologies for customer’s production designs.