Verification IP for UFS

Synopsys Verification IP (VIP) for UFS provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of UFS links operating in high speed and low speed modes.

Native SystemVerilog/UVM based VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences. Time-to-market (TTM) can be reduced with Synopsys UFS Host test suite and UFS Device test suites.

Verification IP for UFS


  • Native SystemVerilog/UVM
  • Source code test suite
  • Runs on all major simulators
  • Verification plan and coverage
  • Built-in protocol checks
  • Synopsys Verdi® Protocol Analyzer
  • Error injection and exceptions

Key Features

  • JEDEC UFS 4.0 (EA), 3.1, 3.0, 2.0, UFS 2.1 (JESD220C), HCI 2.1 (JESD223C), UME 1.1 (JESD220-1A), UMEHCI 1.1 (JESD223-1A)
  • MIPI UniPro 2.0 (EA),1.8, 1.6
  • MIPI M-PHY 5.0, 4.1, 4.0, 3.0
  • CPORT interface
  • RMMI interface with built-in UniPro layers
  • MPHY serial interface with built-in UniPro and MPHY layers
  • UPIU support for NOP Out, NOP In, commands, Response, Reject, Data In/out, Query Request/Response, Ready to transfer (RTT)
  • Multiple outstanding Command UPIU
  • Task Management Request/Response
  • Controllable Logical Unit Command Depth
  • SCSI Commands
  • Resets: Hardware, Endpoint, Host UniPro warm reset, Logical reset
  • Universal Memory Extension (UME) support RPMB
  • Lane-to-lane Skew Injection