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Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

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3 min read/Apr 04, 2025

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Using Synopsys VSO.ai to Accelerate Synopsys VIP and IP Coverage

By Taruna Reddy

Tags: AI & Machine Learning, Debug, Simulation, Verification IP, Verification

Verdi Waveform Utilities: Get More Done with Faster Runtime and Less Memory

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2 min read/Jun 13, 2024

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Verdi Waveform Utilities: Get More Done with Faster Runtime and Less Memory

By Lauren Wu, Robert Ruiz

Tags: Verification Central, Debug, Verification

Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

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3 min read/May 09, 2024

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Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

By Vita Liao

Tags: Verification Central, Debug, Simulation, Verification

SoC Design and Verification Solutions for a New Era of AI Chips

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9 min read/Mar 08, 2024

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SoC Design and Verification Solutions for a New Era of AI Chips

By Kiran Vittal

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification

A Pain in the X! Why Debugging Xs can be Difficult

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5 min read/Feb 07, 2024

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A Pain in the X! Why Debugging Xs can be Difficult

By Myles Gilsson

Tags: Verification Central, Debug, Verification

Streamline Projects with Verdi and VCS Coverage Tools

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2 min read/Jul 12, 2023

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Streamline Projects with Verdi and VCS Coverage Tools

By Taruna Reddy

Tags: Verification Central, Debug, Simulation, Verification, Formal Verification

How Imparé Leverages Chip Design Verification in the Cloud

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6 min read/May 03, 2023

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How Imparé Leverages Chip Design Verification in the Cloud

By Rob van Blommestein

Tags: Customer Spotlight, Cloud, Debug, Chip Design Insights, Simulation, Verification

Optimizing the RTL Design Flow with Real-Time PPA Analysis

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5 min read/Mar 09, 2023

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Optimizing the RTL Design Flow with Real-Time PPA Analysis

By Jim Schultz

Tags: RTL Synthesis, Product Spotlight, Debug, Chip Design Insights, Design, Verification

Enhancing Chip Design Simulation with AI

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4 min read/Feb 15, 2023

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Enhancing Chip Design Simulation with AI

By Taruna Reddy

Tags: AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, Verification

How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

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2 min read/Dec 15, 2022

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How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

By Taruna Reddy

Tags: Verification Central, Debug, Simulation, Verification

Exploring ML-Based Regression Failure Analysis

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3 min read/Nov 15, 2022

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Exploring ML-Based Regression Failure Analysis

By Rob van Bloomestein

Tags: Verification Central, Debug, Verification

Advanced Protocol Standards Verification for SoC Designs

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6 min read/Oct 24, 2022

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Advanced Protocol Standards Verification for SoC Designs

By Vikas Gautam

Tags: Debug, Prototyping, Chip Design Insights, Emulation, Interface IP, Verification IP, Silicon IP, Verification

AI-Driven Debug Automation Speeds Up Root-Cause Analysis

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2 min read/Sep 11, 2022

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AI-Driven Debug Automation Speeds Up Root-Cause Analysis

By Rob van Blommestein

Tags: AI & Machine Learning, Debug, Chip Design Insights, Design, Verification

Enhancing Chip Verification with AI and Machine Learning

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4 min read/Jul 12, 2022

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Enhancing Chip Verification with AI and Machine Learning

By Rob van Blommestein

Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification

Fault Simulation Techniques for Growing Chip Complexity

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6 min read/Jun 01, 2022

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Fault Simulation Techniques for Growing Chip Complexity

By Brian Davenport, Rimpy Chugh

Tags: Customer Spotlight, Aerospace & Government, Debug, Chip Design Insights, Simulation, Automotive, Verification

Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

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4 min read/Mar 20, 2022

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Boosting EDA Workloads with 3rd Gen AMD EPYC™ Processors

By Ramesh Narayanaswamy

Tags: Customer Spotlight, Debug, Chip Design Insights, Simulation, Verification

Accelerating System Debug in the SoC Verification Flow

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4 min read/Jan 17, 2022

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Accelerating System Debug in the SoC Verification Flow

By Swami Venkat, Taruna Reddy

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification

What is Clock Domain Crossing? - ASIC Design Challenges

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7 min read/Nov 22, 2021

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What is Clock Domain Crossing? - ASIC Design Challenges

By Rimpy Chugh

Tags: Debug, Chip Design Insights, Simulation, Verification

Functional Chip Design Verification: When Is It Truly Finished?

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5 min read/Nov 21, 2021

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Functional Chip Design Verification: When Is It Truly Finished?

By Will Chen, Anika Malhotra

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification IP, Verification

Advancing Women in Tech Careers: Q&A with Latha Venkatachari

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7 min read/Nov 10, 2021

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Advancing Women in Tech Careers: Q&A with Latha Venkatachari

By Synopsys Editorial Staff

Tags: Debug, Chip Design Insights, Verification, Inside Synopsys, Formal Verification

ASIC Hardware Verification: Debug Challenges & Solutions

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7 min read/Oct 26, 2021

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ASIC Hardware Verification: Debug Challenges & Solutions

By Kiran Vittal

Tags: Debug, Prototyping, Chip Design Insights, Emulation, Verification, Virtual Prototyping, Formal Verification

RTL Debugging via FPGA Prototyping: SoC Design Challenges

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5 min read/Oct 06, 2021

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RTL Debugging via FPGA Prototyping: SoC Design Challenges

By Rob Parris

Tags: Debug, Prototyping, Chip Design Insights, Verification

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5 min read/Sep 20, 2021

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Upgrading FPGA Prototyping for RTL Debug Productivity

By Rob Parris

Tags: Debug, Prototyping, Chip Design Insights, Verification

Verifying Complex Datapath Designs with HECTOR

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5 min read/Feb 23, 2021

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Verifying Complex Datapath Designs with HECTOR

By Kiran Vittal, Alfred Koelbl, Pratik Mahajan

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification

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