How to Achieve 2X Faster Waveform Dumping in Synopsys Verdi with VCS

If you are a Synopsys Verdi user, what simulator are you using? The answer could have a significant impact on your verification productivity. For example, if you use a non-Synopsys simulator, you may experience longer than normal regression runs when signals are dumped, and in some scenarios the time to load the Fast Signal Database (FSDB) into Verdi increases too. In this blog we’ll share the native integrations that the Synopsys Verdi® debug solution and Synopsys VCS® functional verification solution share that will improve your designs performance and debug productivity. Let’s explore these Verdi and VCS optimizations a bit more.

What is Dynamic Aliasing?

Dynamic aliasing is used to optimize clock intensive designs where multiple clock signals like reset or power related signals have the same activity 90% of the time and the two signals are then aliased for that 90% . This is a distinguishing activity that can reduce unnecessary saved raw data also resulting in increased performance. The integration between Synopsys Verdi and VCS as it applies to dynamic aliasing has been proven to help simulations run 1.5X faster and reduce the FSDB size by 5X.

Native Integrations

A native integration between Synopsys Verdi and VCS includes sharing a common parser and elaborator as seen in the image below. This means that when designers compile for Verdi and VCS, they don’t observe any inconsistencies or need to maintain two separate flows. The simulator and debugger databases are generated in parallel leading to better performance and accuracy. These benefits cannot be leveraged in flows where Verdi is used with other simulators. Verdi used with another simulator will warrant two compile flows leading to inconsistencies (e.g. filelist, compile errors etc.) and additional cycles wasted in debug.

Debugging Your Design

Interactive debug of the testbench including classes, UVM based debug like phases, factory and sequences and constraint debug are some of the powerful debug tools that are exclusive to a Synopsys VCS and Verdi flow. Interactive debug with VCS allows you to go back in time without restarting simulations, enabling the ability to run what-if analysis and achieve full visibility into the testbench.

One of the primary challenges with constraint debug is root-causing the failing constraint, especially in cases where the user is unfamiliar with the source code or the constraint is deep in the code. Using Synopsys Verdi allows its powerful constraint debug solution to provide on-the-fly randomization, eventually evaluating the distribution of stimuli and their impact on coverage closure.

To learn more about the benefits of the unique native integrations between these two tools related to debug, refer to our whitepaper – The Next Generation of Testbench Debug Productivity

Synopsys Verification Solutions

The tight integration between Synopsys’ functional verification solutions – Synopsys VCS, Synopsys Verdi, and Synopsys VC Formal™ –  delivers the speed, capacity, and flexibility to verify today’s complex SoCs and get to the bottom of root causes of design bugs.

Synopsys silicon design and verification solutions share common technologies and consistent design interpretation that provide verification engineers with a seamless user experience, higher performance, and increased productivity. Continued innovation in “value links” across Synopsys products enables companies to efficiently design the next wave of transformative products.

Stay tuned for future blog posts exploring how the connections between Synopsys’ functional verification solutions help to improve and productivity.