Interactive Debugging: Reduce Your Simulation Debug Turnaround Time

Vita Liao

May 09, 2024 / 3 min read

For most verification engineers, the day starts with understanding and solving yesterday's regression failures. After a nightly regression run, there are usual and customary steps that are taken. Routine tasks include querying failed tests, re-generating the debug database, re-running simulations for more information and also ensuring the correctness of different functional scenarios and testing patterns. Each stage often considerable time commitment and sometimes requires several iterations, lengthening the entire debug process.

To address this challenge, the next-generation Synopsys Verdi® debug platform provides capabilities that assist with avoiding the need to go back and forth among the different steps. However, many users have questions about the process of repeating simulations. This blog reviews considerations verification engineers might have throughout the process and explains how users can take advantage of Verdi features during interactive mode to reduce repeated operations and reduce the time for root cause analysis.

After a nightly regression, I want debugging files ready the next morning.

This is definitley possibly with a feature called "Verdi instant recall". As the regression runs, Verdi instant recall interacts with Synopsys VCS® and provides debugging information to debug any failed test cases. The debugging information specifies which error occurred and where. This information is very helpful for clarifying the error category and where to start debugging without the need to manually rerun the simulations for additional debug data generation. 

Synopsys Verdi Instant Recall - Reduce Regression Debug TAT

During a debug session I want to run ‘what-if’ experiments but I want to avoid recompiling and rerunning simulation.

After enabling Verdi interactive debug mode, several on-the-fly modifications are made available for users to setup and validate experiments in a single simulation. Some of modifications including simulation stimulus, updating random configurations and re-randomization are accomplished with Verdi’s what-if analysis on a single simulation. Verdi also provides visibility for the interactive analysis of the SystemVerilog constraint solver’s solution space through on-the-fly generation of probabilistic distributions of random values (without the dependency for pre-existing coverage observer code). This capability also allows fine tuning the stimulus to cover functionally with a range of interesting values for debug more quickly.

During a debug session I would like to see how the values changed at previous points in time and observe changes with more experiments.

With Verdi you can accomplish that with the reverse debug mechanism. Typically a user might go about achieving this is by adding some debug simulation flags for the interested point and restarting the simulation to stop at the point in time noted by the flag. In Verdi interactive mode, there is an extremely high degree of freedom allowed to control the simulation going backward or forward to any point that you specify, including towards an event, object creation, or value change.

Synopsys Verdi Instant Recall - Reduce Regression Debug TAT

In addition, these useful features can be used together to speed-up your debugging flow. For example, after a regression is completed with the instant recall feature the user can then select failed cases based on the error type and immediately use the generated debugging database to launch Verdi to debug. During the debugging, if the value of a signal in the previous time point needs to be recalled, the reverse debug feature could be used to navigate the simulation. Also, the user could re-randomize with a different configuration to observe probabilistic distributions. 


As outlined in this blog, Synopsys Verdi debug platform is feature rich to boost debug productivity. When engineers start their mornings ready to debug, the capabilities that the Verdi provides allows them to get started quickly. All the features shared in this blog help to avoid the time-consuming need to re-compile and re-simulate. Leverage one simulation to decrease your debug turn-around-time!

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