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Formal Verification

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Top Writers

Jin Zhang

Rimpy Chugh

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Reducing Errors and Iterations with an Enhanced Timing Constraints Signoff Flow

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3 min read/Mar 26, 2024

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Reducing Errors and Iterations with an Enhanced Timing Constraints Signoff Flow

By Naveen Battu, Rimpy Chugh

Tags: Static Verification, Product Spotlight, Chip Design Insights, Verification, Formal Verification

SoC Design and Verification Solutions for a New Era of AI Chips

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9 min read/Mar 08, 2024

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SoC Design and Verification Solutions for a New Era of AI Chips

By Kiran Vittal

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification

Synopsys Users & Experts Come Together Again for Annual VC Formal SIG Event

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7 min read/Oct 01, 2023

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Synopsys Users & Experts Come Together Again for Annual VC Formal SIG Event

By Yann Antonioli

Tags: Verification Central, Verification, Formal Verification

Streamline Projects with Verdi and VCS Coverage Tools

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2 min read/Jul 12, 2023

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Streamline Projects with Verdi and VCS Coverage Tools

By Taruna Reddy

Tags: Verification Central, Debug, Simulation, Verification, Formal Verification

AI & Math Core Verification: Datapath Validation

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3 min read/Jun 25, 2023

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AI & Math Core Verification: Datapath Validation

By Jin Zhang

Tags: Verification Central, Verification, Formal Verification

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6 min read/May 08, 2023

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How to Shift Verification Left in Low-Power Chip Design

By Avinash Palepu

Tags: Static Verification, Product Spotlight, Chip Design Insights, Energy-Efficient SoCs, Verification, Formal Verification

How Formal Verification Tools Enhance SoC Simulation Coverage

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4 min read/Nov 20, 2022

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How Formal Verification Tools Enhance SoC Simulation Coverage

By Jin Zhang

Tags: Product Spotlight, Chip Design Insights, Simulation, Verification, Formal Verification

How to Protect Advanced Chip Designs from Security Breaches

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5 min read/Nov 09, 2022

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How to Protect Advanced Chip Designs from Security Breaches

By Ian Land

Tags: Aerospace & Government, Silicon Lifecycle Management, Prototyping, Chip Design Insights, Simulation, Design, Emulation, Silicon IP, Verification, Formal Verification

What is Code Linting? - Advanced Linting & SoC Design (Part 1)

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5 min read/Oct 26, 2022

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What is Code Linting? - Advanced Linting & SoC Design (Part 1)

By Rohit Kumar Ohlayan, Himanshu Kathuria, Rimpy Chugh

Tags: Static Verification, Chip Design Insights, Verification, Formal Verification

Power-Aware Clock Domain Crossing with STMicroelectronics

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5 min read/Aug 23, 2022

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Power-Aware Clock Domain Crossing with STMicroelectronics

By Deepak Ahuja, Navneet Kumar Chaurasia

Tags: Customer Spotlight, Static Verification, Chip Design Insights, Verification, Formal Verification

Enhancing Chip Verification with AI and Machine Learning

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4 min read/Jul 12, 2022

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Enhancing Chip Verification with AI and Machine Learning

By Rob van Blommestein

Tags: Multi-Die System, Static Verification, AI & Machine Learning, Product Spotlight, Debug, Chip Design Insights, Simulation, HPC, Data Center, Verification, Formal Verification

Formal Verification Services Ramp Up SoC Design Productivity

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5 min read/Jun 21, 2022

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Formal Verification Services Ramp Up SoC Design Productivity

By Jin Zhang

Tags: Chip Design Insights, Verification, Formal Verification

Leveraging Static Linting Tools - ASIC Design Challenges

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7 min read/May 10, 2022

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Leveraging Static Linting Tools - ASIC Design Challenges

By Rohit Kumar Ohlayan, Rimpy Chugh

Tags: Static Verification, Chip Design Insights, Verification, Formal Verification

Formal Chip Design Verification in the Cloud: EDA Tools

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6 min read/Nov 15, 2021

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Formal Chip Design Verification in the Cloud: EDA Tools

By Pratik Mahajan, Ahmed Elzeftawi

Tags: Cloud, Chip Design Insights, Verification, Formal Verification

Advancing Women in Tech Careers: Q&A with Latha Venkatachari

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7 min read/Nov 10, 2021

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Advancing Women in Tech Careers: Q&A with Latha Venkatachari

By Synopsys Editorial Staff

Tags: Debug, Chip Design Insights, Verification, Inside Synopsys, Formal Verification

ASIC Hardware Verification: Debug Challenges & Solutions

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7 min read/Oct 26, 2021

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ASIC Hardware Verification: Debug Challenges & Solutions

By Kiran Vittal

Tags: Debug, Prototyping, Chip Design Insights, Emulation, Verification, Virtual Prototyping, Formal Verification

How Emulation Helps Find Power Bugs During SoC Verification

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5 min read/Jul 06, 2021

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How Emulation Helps Find Power Bugs During SoC Verification

By Alex Wakefield

Tags: Static Verification, Chip Design Insights, Simulation, Design, Emulation, Energy-Efficient SoCs, Signoff, Verification, Virtual Prototyping, Formal Verification

Verifying Complex Datapath Designs with HECTOR

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5 min read/Feb 23, 2021

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Verifying Complex Datapath Designs with HECTOR

By Kiran Vittal, Alfred Koelbl, Pratik Mahajan

Tags: AI & Machine Learning, Debug, Chip Design Insights, Verification, Formal Verification

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2 min read/Jun 19, 2018

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Managing Initial State in Formal Verification for Optimal Results

By Synopsys Editorial Staff

Tags: Verification, Formal Verification

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1 min read/Aug 16, 2017

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Phalanx Strategy: Applying Greek Warfare Tactics to Formal Property Verification

By Synopsys Editorial Staff

Tags: Verification, Formal Verification

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