Showcasing AI-Driven Analog Design Migration at Samsung SAFE Forum

Neel Gopalan

Nov 02, 2023 / 6 min read

Earlier this year, I had the opportunity to attend and present at Samsung SAFE Forum (SFF) in San Jose, California, during the “Advanced Technology and Design Infrastructure” session. The session started with a Tech Talk delivered by Sangyun Kim, VP and head of Design Technology, Samsung Electronics, who artfully articulated several important technology insights and trends: advanced FinFET technology and the Samsung technology roadmap, 3D IC and multi-die integration, and design migration solutions to help customers quickly take advantage of the most optimized Synopsys technologies for their applications. Later, the session included partners presentations, which is where I came in.

My presentation titled “Accelerating Analog and Digital Design Migration Using” focused on one of Samsung’s key topics: rapid analog design migration challenges. I started my talk by highlighting several key high-value problems our customers and partners are telling us they need help with:

  • Rapidly migrating designs to new process technology nodes to keep up with the industry’s relentless and continuous push forward
  • Using multi-die integration to extend Moore’s law into the SysMoore era
  • Getting to market quickly by ensuring first-time-right silicon
  • Delivering highly robust electronic systems, especially for mission-critical applications 

Rapidly Migrating Designs to New Process Technology Nodes

As described in an earlier post “Accelerating Analog Design Migration,” automation has always been a challenge in the analog design world, and analog design migration in particular has been very difficult to automate.

With the introduction of artificial intelligence (AI), machine learning (ML), and big data, however, we now have a way to help our customers and partners to rapidly migrate and optimize analog designs in their target technology node. To illustrate Synopsys’s solution, I discussed a case study involving Samsung Foundry.

Case Study: Migrating a Bandgap Design from Samsung 14nm Node to Samsung 5nm Node

In this example, the design is a voltage bandgap reference (VBGR) circuit on Samsung Foundry’s 14nm technology that needed to be migrated to a Samsung 5nm node.

Implementing this bandgap design at 5nm would typically involve the following steps:

  • Capture or migrate schematics
  • Simulations and design centering across selected process, voltage, and temperature (PVT) corners
  • Layout implementation, typically from scratch
  • Validate that the design still performs correctly when layout parasitics are incorporated in post-layout simulations

What happens if the post-layout simulation fails? The design and layout teams would be in an implementation-extraction-simulation loop until converging on an optimal point. This is a very manual, iterative, and labor-intensive process.

analog ic design migration process

AI-Based Analog Design Migration

When we looked at the entire analog design migration flow with the understanding that layout effects must be taken into consideration early, as part of the design-centering and optimization steps, we knew we needed to develop a far more integrated solution than what is available to engineers today. Furthermore, understanding there are complex dependencies between multiple design parameters, PVT corners, and testbenches to meet a specification with several objectives and measurements, we concluded that existing optimization techniques already available in the market are not sufficient for solving and optimizing such a large design space challenge.

Therefore, we built a new AI-based automation solution to rapidly migrate schematics and layout to a new technology node and perform design optimization of the migrated design, taking into consideration the layout effects as it optimizes across hundreds of corners and test. The intent was to achieve design convergence faster, in fewer iterations, and with minimum human effort. 

ai analog circuit design migration flow

Let’s review Samsung’s bandgap design and highlight the three majors components we developed for the analog design migration solution in Synopsys Custom Compiler:

Automatic schematic migration: The automated schematic migration capability in Custom Compiler starts with a one-time setup to define the mapping of devices and parameters between Samsung 14nm process design kit (PDK) and Samsung 5nm PDK. Mapping between source and target technologies is established for devices, parameters, layers, and vias. We used this utility to automatically migrate the complete hierarchical bandgap schematics to the 5nm PDK.

ML-based automatic layout migration:  Our solution can automatically generate a new layout at 5nm that will look very similar to the 14nm original design, while complying with the 5nm design rules. We first run layout-versus-schematic (LVS) using Synopsys IC Validator to make sure we have proper mapping between layout and schematic. This step relives the requirement for the original 14nm design to be schematic-driven layout (SDL) compliant, and Custom Compiler automatically takes care of connectivity and device mapping in both the reference 14nm design and in the newly migrated 5nm design.

integrated circuit design migration

AI-based design optimization: Once the design was migrated to 5nm, we used Synopsys PrimeWave AI-based design optimization solution to center the design across all 360 PVT corners and multiple tests.
Based on the designer’s input, a set of devices and device parameters was chosen for the optimizer to manipulate, and the bandgap specification will be used as matrices to achieve. Parasitic data from the migrated layout can be added for the optimizer to consider as part of its job.

The results: Design optimization that completed in hours versus in days.

The bandgap design was optimized across all 360 PVT corners in under three hours. The turnaround time (TAT) benefit is obvious: getting a task done in a few hours versus days provided a substantial productivity boost and resulted in superior design results.

Layout Migration Details and Post-Layout Verifications

The bandgap circuit has very strict requirements for matching. Using the migrated schematics and topologies and the layout structures that were extracted from the bandgap design in 14nm node, we were able to truly migrate (not simply regenerate) the layout at the new 5nm node. Custom Compiler was able to detect and “learn” analog placement and matching patterns for the FinFET transistors, resistors, capacitors banks, and bipolar devices. The placement and the routing engines were tuned to “learn” and follow the original topologies that were present in the original 14nm layout. Dummy devices, guard rings, and tap cells were added to comply with the 5nm design rules.

As part of this exercise, we migrated the 14nm bandgap design to both 8nm and 5nm nodes. As you can see from the picture below, the placement and layout topology looking very similar in all three layouts. 

semiconductor manufacturing process node

As we all know, placement is half of the layout migration challenge. So, how does the routing migration look across all three nodes?

place and route migration

In the above snapshot, you can see the similarity of routes in all three nodes. Once the design was migrated to 5nm, minimal manual clean-up was required to get the design ready for signoff verification.
Once the design was LVS clean, I was able to extract parasitics using Synopsys StarRC extraction solution and validate post-layout simulation results.


At Samsung SAFE Forum, Samsung Foundry and many of our mutual customers highlighted the importance of having a design migration solution, and analog design is no exception.

The Synopsys AI-driven analog design migration solution consists of three major components:

  • Automated schematic migration utility
  • ML-based layout migration solution
  • AI-based design optimization solution

We used our comprehensive migration solution to migrate a bandgap design from Samsung 14nm technology to 8nm and then to 5nm, all Samsung Foundry nodes. All design specifications were met using the AI-based optimizer in Synopsys PrimeWave design environment and across 360 PVT corners. The design was validated in post-layout simulation and passed all signoff checks. In addition, the solution works across hierarchies and in a mixed design of transistors, passives, and other macro-blocks.

Thank you to Samsung Foundry for giving us the opportunity to demonstrate our solution at the Samsung SAFE Forum.

Continue Reading