Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Table of Contents
From automated assembly line equipment that falters to laptops that continually crash, a variety of electronic system issues can be traced back to chip failures caused by electrostatic discharge (ESD). In fact, more than 30% of semiconductor failures stem from ESD and such failures can be even more damaging when they impact safety-critical applications, such as a vehicle’s automated braking system. So, anything you can do to bring this percentage down would be beneficial for end application users as well as your bottom line.
Until now, it’s been difficult to get a reliable, exhaustive analysis of all ESD events across the entire chip. Solutions on the market have only been able to perform static analysis, limited in their ability to simulate the true transient nature of ESD. Yet, designers need to have confidence that their ESD protection devices are reliable and not any larger than they should be.
Now there’s new technology for you to build in reliability against all ESD events in your silicon chips: Synopsys PrimeESD full-chip ESD analysis solution. PrimeESD improves turnaround time and reliability by delivering exhaustive analysis of all ESD events across the chip and package. Its advanced algorithms and simulation techniques analyze ESD protection structures within an IC design. Read on to learn how the solution can help increase designer productivity and improve your design’s reliability.
Why Exhaustive ESD Protection Analysis Is Critical
As chips grow larger, it becomes harder for simulation and analysis solutions to handle the full chip. After all, nanometer designs contain billions of devices. (Ironically, ESD protection circuits themselves could be overdesigned, leading to large die sizes.) With larger chips, transient effects cause more failures. Inductance, capacitance, snapback devices, and larger packages all affect the behavior and need to be modeled to correctly simulate the design. Today’s static ESD checkers are a valuable part of the reliability analysis equation; however, they don’t account for these effects. Reporting of false violations can happen, costing designers time by debugging problems that don’t exist. For example, while decoupling caps improve reliability, they can cause false positives in static tools. To be fair, foundries have done some very clever things to enable some manner of charged-device model (CDM) checking with static checkers. But the industry needs something more comprehensive.
Exhaustive analysis of everything is critical to pinpoint every possible ESD problem, for both HBM (human body model) and CDM events. HBM is the discharge when an individual touches the device. A CDM event happens when a charged device contacts a grounded object. Regarding HBM, the package is sometimes used to reduce the resistive path, while in CDM, the package increases the charge distribution area. Both scenarios require inclusion of the package for correct simulation.
The time that it takes to attempt an exhaustive analysis of a chip also explodes as chip sizes grow. Imagine the challenges with today’s multi-die systems, given all their layers of interdependencies! This is where distributed analysis—taking advantage of parallel processing by distributing the run over multiple CPUs—provides an advantage in turnaround time and coverage.
Full-Chip ESD Analysis Solution Goes Where No Other Tool Has Gone
PrimeESD changes the ESD analysis game, providing a full solution that exhaustively and swiftly analyzes the full chip. It verifies core and protective ESD devices, the interconnect, and the package. It highlights EM violations and devices that may be susceptible to ESD damage, simulates every HBM and CDM event, and automatically generates reports of current density violations and high-resistance paths. The full-chip ESD analysis solution eliminates false violations. Developed with distributed analysis capabilities, PrimeESD can run a multi-billion-transistor design in about a day. So far, the largest design it has handled contained 15 billion transistors.
To design for ESD reliability, the ESD flow should follow a series of steps that are aligned with steps in the design flow. The PrimeESD solution supports each of these steps.
- Floor planning: Verify power clamp and ESD path interconnect robustness; identify ESD devices that are unused or lightly used
- IP block layout: Verify IP-level ESD device and interconnect reliability
- Complete layout: Simulate the full chip to highlight HBM and CDM issues
The combination of PrimeESD with its powerful ability to handle dynamic effects, along with Synopsys IC Validator™ PERC static checking solution, provides a well-founded duo to tackle ESD requirements.
Summary
With nearly one-third of semiconductor failures stemming from ESD, the payoff to finding and resolving these problems early on is huge. Static checkers, however, are limited in uncovering all the ESD issues. PrimeESD full-chip ESD analysis solution turns a frustrating process into a highly productive one, complementing static checkers to deliver exhaustive and swift ESD analysis of the entire chip and package. With these capabilities in the mix, you can optimize your designs and put an end to potentially devastating design issues.