Explore challenges and solutions in AI chip development
Systems-on-chip (SoCs) and chiplet-based semiconductors continue to grow in complexity. With multi-die architectures, AI accelerators, and increasing memory bandwidth becoming the norm, it’s more important than ever to address performance and power early in the design cycle.
Traditional architecture exploration approaches like spreadsheets, RTL simulation, and ad hoc communication are slow and manually intensive, often resulting in fragmented workflows and delayed feedback. Simply put, these antiquated methods can no longer support today’s pace of silicon innovation.
To streamline early-stage architecture exploration, we recently introduced the Synopsys Platform Architect Development Kit (PADK), a web-based collaboration framework that extends the proven capabilities of Platform Architect into a more accessible, interactive, and role-based environment for architecture design teams.
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Platform Architect is a SystemC, TLM-based virtual prototyping environment for pre-RTL architecture exploration. By simulating the performance and power characteristics of SoC and chiplet workloads, Platform Architect has become a vital tool for design teams developing silicon for AI, automotive, and high-performance computing (HPC) applications.
A lightweight, web-based extension of Platform Architect, the new PADK further improves architecture exploration through structured, role-focused collaboration.
PADK addresses three persistent challenges in pre-RTL system design:
With PADK, users access a secure, web-based interface that facilitates real-time collaboration without requiring deep simulation expertise. Customizable dashboards present important performance metrics (e.g., latency, power, and area), while role-based access control guarantees users view only the data relevant to their responsibilities.
Uploaded documentation — including AI graphs and trace files — is encrypted, allowing customers to evaluate performance without exposing sensitive data. And because PADK supports in-browser simulation, users can easily tweak parameters or explore alternative configurations without waiting for modeling teams.
By unlocking frictionless data sharing, fast simulation and iteration, and cross-team alignment, PADK delivers a more agile and collaborative approach to SoC and chiplet architecture exploration and performance analysis.
The standard PADK workflow is as follows:
Though applicable across industries, PADK is particularly valuable in fast-evolving sectors like automotive, AI acceleration, and HPC. Ultimately, it helps teams make better architectural choices, faster.
PADK reshapes how architecture teams explore and align around early design decisions by removing long feedback cycles and unlocking more agile interaction.
Synopsys PADK brings early architecture exploration into the cloud and transforms it from a siloed, manual process into a fast, secure, and collaborative experience. By bridging the gap between architects and stakeholders, it facilitates faster, more informed decisions and shorter development cycles.
Whether you're optimizing SoC bandwidth or validating chiplet configurations, PADK makes it easier to explore, iterate, and share.