How to Shift Verification Left in Low-Power Chip Design

Avinash Palepu

May 08, 2023 / 6 min read

As the semiconductor industry moves toward smaller process nodes, static power has become a primary design constraint. This has necessitated development of various power management techniques. For example, designers might create multiple voltage domains or use isolation cells to isolate a shut-down power domain from a powered-on domain. They might apply a level shifter to scale signal voltages up or down as they propagate from one domain to another, or use retention cells for faster return of a register to its state before shut down. Like a hardware description language (HDL) to specify functional intent of a design, implementing these techniques requires a common language to specify the design’s power intent: Unified Power Format (UPF).

Considering how highly complex and often specific to an application today’s SoCs are, the effort that goes into designing and achieving desired functionality along with timing and power requirements is enormous. But merely meeting these goals is not enough. The end user’s insatiable desire for the latest features in the shortest amount of time creates pressure on the IP development team. In order to meet time-to-market goals, chip design companies often adopt a parallel development approach where different teams write register-transfer level (RTL), Synopsys Design Constraints (SDC) files, UPF files, and so on.

Even though the development of the design and UPF go hand in hand, their schedules might vary, which can lead to some challenges. In this blog post, I’ll explain how you can overcome these challenges with Synopsys VC LP™ Design-Independent UPF Checker (VC UPF). Read on to learn how VC UPF lets you clean up design-independent issues in the UPF file even before RTL is ready.

Central Computer Processors CPU concept

Optimizing Your SoC Design for Power

When designing an SoC, the first version of UPF might be ready even before RTL is finalized. The accuracy and completeness of UPF cannot be verified unless the design is ready. So, there is often a window where the engineer writing the UPF is simply waiting for closure on the first cut of the RTL. Once the design is ready, the engineer runs a static checker tool to validate the UPF with respect to design and that’s when he or she realizes that there are some basic issues in the UPF which could have been caught even without reading the design. Unfortunately, some time has already been lost in this process. Multiple iterations of UPF fixing and checking lead to long turnaround times!

This is where VC UPF comes to the rescue.

VCS UPF Diagram

As the name suggests, VC UPF enables the power intent owner to clean up design-independent issues in the UPF file even before RTL is ready. The solution covers:

  • UPF syntax and semantic checks
  • UPF supply analysis-based checks
  • PST consistency checks
  • UPF network-related consistency checks
  • Methodology-specific checks based on allowed/disallowed commands and options

Let’s look at a few examples to understand how this could help.

Consider a scenario where a UPF supply net does not have any power state defined. It is only after reading the design, loading the UPF, and completing the UPF checks that the user will realize that, due to the missing state, there are some crossovers for which no analysis can be done. With VC UPF, this information will be available within a few minutes.


In another scenario, the isolation supply net for the isolation strategy may not be available in the desired domain.

VC LP Flow

Here’s another example. Consider the path from PD3 to PD2. There is no electrical issue as the OFF–>ON crossing is correctly protected by an isolation cell. So traditional electrical checks do not flag any violation. But in the same scenario, there is a functional issue that the signal from PD1 is blocked by the combo in PD3 which has supply OFF.

Power Intent

The new advance checks in VC LP flag the issue correctly and alert the designer that though the path is correctly isolated, the signal from PD1 is blocked by combo in OFF domain and only a clamp value will reach PD2.

Crossing Analysis

Based on the violation, the designer should verify whether the path is intended to carry functional information during the indicated power state. If it is not function in the given power state, then no further action is needed. On the other hand, if the path was functional, then the indicated buffer/inverter/combo needs to be powered on and the supply connection to the combo needs to be fixed. Identifying these issues through simulation is time-consuming but with VC LP, you can now catch these issues early in your design cycle and save time in simulation.

Although the main motivation of VC UPF is an early cleanup of UPF, it can also be used for UPF management for an SoC. Complex SoCs have UPF files for IP blocks from different vendors/groups, which often results in late UPF modifications and delayed schedules and re-verification. To avoid this, CAD teams may enforce some guideware rules to comply with UPF deliverables for IP vendors to enable smooth SoC Integration. VC UPF can help perform such guideware UPF construct checks using disallow_* commands or allow_* commands.

Similarly, during SoC integration, you might not want a particular IP-level UPF TCL variable to be overwritten from the top. A standard UPF with design checking tool will never recognize this as a problem. But with VC UPF, you can specify the list of such protected variables and quickly find out if any of them have been overridden from a top-level UPF. You can also verify the compatibility of the UPF version of an IP with respect to the SoC UPF. Depending on the user guidance regarding which UPF version combinations are allowed and disallowed, VC UPF can perform IP versus SoC consistency checks. Note that otherwise, VC LP is UPF version-agnostic and “upf_version” has no consequence.

Production-Proven, Power-Aware Static Checking Signoff

The Synopsys VC LP solution, which provides accurate and production-proven support for UPF, is tightly integrated with other tools for static low-power checking and debug:


It goes without saying that it takes a lot of effort to design low-power SoCs that meet the desired functionality, timing, and power requirements. The undertaking comes under stringent time-to-market pressures, too. Often, chip design companies opt for a parallel development approach in which different teams write RTL, design constraint files, UPF files, and so forth. But while the development of the design and UPF may go hand-in-hand, their schedules could vary.

The VC LP solution enables the power intent owner to clean up design-independent issues in the UPF file before the RTL is ready. The solution can also be used for UPF management for an SoC, as complex SoCs typically have UPF files of IP from different vendors, which can result in late UPF modifications and delayed schedules and re-verification. With the ability to clean up UPF early on, engineers can save time and effort in their low-power SoC design cycle.

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