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Smarter Signoff Video Series
Smarter Signoff Technologies and Methodologies
New functionality that improves performance, productivity and schedule predictability.
- PrimeTime: Golden timing signoff including static timing, signal integrity, power and timing constraint analysis
- StarRC: Industry leading parasitic extraction for digital and custom design
- Silicon Smart: Advanced cell characterization solutions
Smarter Library Voltage Scaling with PrimeTime
Smarter Waveform Analysis with PrimeTime
Smarter Hierarchical Signoff with HyperScale 2nd Generation
Smarter LVF characterization with SiliconSmart ADV
Smarter PrimeTime Power ECO
Smarter and Faster Galaxy Incremental ECO
Smarter Late-Stage Signoff with PrimeTime’s Freeze Silicon ECO
Smarter, Resource Efficient ECO
Smarter System-on-Chip Signoff with Multiply Instantiated Module Support
Smarter Parasitic Extraction for Faster Multi-Corner Turnaround Time
Smarter Characterization with SiliconSmart ADV All-In-One Product
Featured Video: Smarter Library Voltage Scaling with PrimeTime
Designs outside of library voltage corners supplied by the foundry can require expensive and time consuming effort to obtain the correct library. Eliminating the need for a library for each specific design corner is a much smarter approach. See how PrimeTime now provides more accurate library voltage scaling technology to eliminate this effort and reduce schedule risk, even at (ultra) low voltages.
Additional Resources
PrimeTime:
Webinar: Multiply Instantiated Module (MIM) Timing Closure with PrimeTime ECO (SolvNet login required)
Broadcom Presentation from PrimeTime SIG at DAC 2015 (SolvNet login required)
Press Release: Synopsys' PrimeTime Speeds Timing and Power Closure for Complex SoC and IoT Designs