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Design Articles
If These Chips Could Talk: Actionable Insights From Path Margin Monitors
April 14, 2022 - Getting feedback during chip bring up, production test, and deployment within end products. One of the most important current trends in electronics is the gathering and analysis of big data to reap benefits in cost, power, performance, and reliability. This is becoming common in the chip development flow.Learn More
Overcoming The Growing Challenge Of Dynamic IR-Drop
Integrating IR signoff within the place and route stage to reduce costly manual ECOs.Learn More
Use Existing High Speed Interfaces for Silicon Test
March 14, 2022 - The growth of complexity for silicon test as it relates to test data volume and test times is driven by multiple concurrent factors. One dimension is simply the increase in silicon complexity. However, other factors are playing a role as well. These include higher reliability requirements for new applications such as automotive, aerospace and defense.Learn More
A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
March 8, 2022 - Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package.Learn More
Is A Guestimate Good Enough For Obtaining Failure Mode Distribution?
Feb. 8, 2022 - Reducing subjectivity and errors when performing functional safety analysis.Learn More
