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Design Webinars
Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
Jun 23, 2020 - In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final signoff.Learn More
Static Timing Signoff and Model Generation for Complex Analog Mixed-Signal Designs Webinar
May 13, 2020 - This webinar discusses a timing signoff methodology that uses transistor-level static timing analysis to augment dynamic simulation. This methodology performs validation for all timing checks (I/O timing, internal timing) including signal integrity effects (crosstalk delay and noise) and parametric on-chip variation (POCV). It discusses how static timing can be used to quickly create block-level timing models (.lib) so that that AMS IP blocks can be used by a digital implementation flow.Watch Now
Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion Designs
Apr 9, 2020 - Watch this webinar to learn how to prevent and eliminate IR drop and power integrity issues using RedHawk Analysis Fusion.Learn More
Achieving Design Robustness in Signoff for Advanced Node Designs
Mar 26, 2020 - This webinar talks about some of the new techniques available from EDA tools such as StarRC to tackle advanced node hierarchical physical design challenges from an interconnect perspective.Learn More
High Speed Ethernet PHY IP Design Methodology Optimization using Custom Compiler
Nov 20, 2018 - This webinar describes how the Synopsys Mixed-Signal IP team optimized their design methodology in a single custom design platform to meet the circuit design, simulations, layout and physical verification requirements of their DesignWare 56G Ethernet PHY IP.Learn More
