A hyper-convergent design flow allows widespread and easy sharing of front-end and back-end data in a unified design process to address these challenges. The process of using late-stage information to inform decisions made early in the design process is called a shift-left approach.

As semiconductor process technology becomes more advanced, physical effects such as wiring delay and voltage drop, electromigration, signal integrity, crosstalk and process variability have become much stronger and have a significant impact on the performance of the resultant design.

This presents a significant challenge for a traditional design flow that begins with front-end logical design and then proceeds to back-end physical design. If the front-end process doesn’t take into account the impact of back-end effects, there will be many iterations between front-end and back-end design. This results in a longer and more costly design process that impacts time-to-market for the end product.

How Does a Hyper-Convergent Design Flow Work?

A hyper-convergent design flow relies on a common data model that is shared by all the tools in the design flow. Using this common data model, it becomes much easier to share information between different phases of the design to implement a shift-left approach and reduce design iterations and time-to-market.

Once a common data model is used pervasively by all the tools in the flow, it is also possible to implement a unified shell in which all the tools operate. This unified shell now allows the design team to integrate flow sequences and data sharing that is specifically targeted at the unique needs of their project. This is called a customer-developed hyper-convergent design flow.

Importance of a Hyper-Convergent Design Flow

A hyper-convergent design flow facilitates the highest possible efficiency to develop advanced semiconductor devices. Without an approach like this, the time and cost to develop these chips becomes prohibitive. A hyper-convergent design flow ensures that advanced semiconductor technology can be put to use in a cost-effective and practical manner.

Benefits of a Hyper-Convergent Design Flow

A hyper-convergent design flow reduces design cost and time-to-market for the end product that is using the chip being designed. These factors can have a substantial impact on the lifetime profitability of the system. This benefit accrues in two ways. First, reducing design costs increases the profit margins on the chip. And second, getting a product to market earlier potentially increases its market share and can lead to higher revenues over the life of the product.

A hyper-convergent design flow also opens the opportunity to create a unified shell in which the tools operate. This unified shell, in turn, allows the end customer to build the exact flow with front-end/back-end data sharing for their unique process. This customer-defined hyper-convergent design flow enables the highest level of efficiency and predictability for an advanced design project.

Hyper-Convergent Design Flow and Synopsys

Synopsys Fusion Compiler™ delivers a singular RTL-to-GDSII digital implementation solution with a common data model.

Fusion Compiler provides an innovative RTL-to-GDSII flow that enables a new era in digital design implementation. The solution offers new levels of predictable quality-of-results to address the challenges presented by the industry’s most advanced designs. Its unified architecture shares technologies across the RTL-to-GDSII flow to enable a hyper-convergent design flow that delivers 20% better quality-of-results and 2x faster time-to-results.

Benefits of this technology include:

  • Single, integrated data model architecture for unmatched capacity, scalability, and productivity
  • Unified RTL-to-GDSII optimization engines that unlock new opportunities for best performance, power, and area results
  • Built-in signoff timing, parasitic extraction, and power analysis to eliminate design iterations
  • Pervasive parallelization with multi-threaded and distributed processing technologies for maximum throughput
  • Leading foundry process certified FinFET, gate-all-around, and multi-patterning aware design

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