Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Enhancing its constraints closure flow for digital designs, Synopsys has acquired FishTail Design Automation, the golden timing constraints company based in Lake Oswego, Oregon. With the September 16, 2022, acquisition, Synopsys now provides a unified, one-stop constraints generation, verification, management, and signoff solution in the Synopsys Digital Design Family of products.
Timing constraints are becoming increasingly complex, which impacts the quality-of-results in terms of power, performance, and area (PPA), design closure time (when the constraints aren’t met), as well as overall time-to-market. FishTail Design Automation, which has been a long-time Synopsys partner, provides a market-leading solution for end-to-end RTL-to-signoff constraints generation and verification (validating constraints in the least noisy manner). Its technologies can continue to be used in a standalone manner and, over the course of the next year, will be tightly integrated into Synopsys’ digital design flow.
As Synopsys welcomes the newest team members into our family, we also wanted to find out more about the merging of our constraints technologies and how design engineers will benefit. For insights, we recently sat down for a discussion with Jacob Avidan, senior vice president of Engineering for the Synopsys Silicon Realization Group.
Q: First off, let’s provide some context: Why has managing timing constraints become more difficult?
A: Chip designs have become more complex, making it even more imperative to provide accurate physical constraints in areas that include timing. Timing is impacted by many external elements, such as integration with other blocks, floor planning, and routing. Timing constraints need to be carefully managed through the design flow; they go through many iterations and must be handed off to the next step in a manner that preserves the design intent. Again, it goes back to the importance of accuracy. When a design team has to manage handoffs between disparate tools from different vendors, however, the process of ensuring that everything is in sync only becomes that much more challenging because of the growing number of clocks and chiplets, and the ensuing hierarchical constraints complexity.
Q: What does FishTail bring to the table?
A: FishTail’s solutions enable generation of clock constraints and timing exceptions, formal constraint verification and interactive debug, and checking, mapping, promotion, demotion, and equivalence verification. The company’s SDC generation solution reads the RTL for a design and generates clock definitions, I/O delays, clock groups, clock senses, and timing exceptions for the design.
Its SDC verification flow reads the RTL description for a design, along with either gate or RTL-level Tcl constraints. Constraints are mapped to the design, with syntax and constraint application issues flagged, and formally proven. The SDC verification technology eliminates the need for gate-level simulation.
Q: What will this acquisition enable Synopsys to offer to the digital design community?
A: Synopsys will be able to accelerate our vision of providing customers with a one-stop, unified RTL to gate-level constraints handling solution that delivers superior constraints closure flow from verification to implementation to signoff. By comparison, many of today’s flows are fragmented, requiring multiple EDA tools and spreadsheet-based internal methodologies. Ultimately, we’ll be able to help customers address the significant productivity and PPA challenges they’re facing due to the escalating complexity of handling timing constraints. Bringing RTL and gate-level timing constraints management together into a consistent timing constraints backbone complements what we’ve done in fusing synthesis, placement and routing, and signoff technologies in the Synopsys Fusion Compiler™ RTL-to-GDSII design product.
Our platform is now enhanced with FishTail’s consistent timing constraints backbone for single-pass constraints closure, addressing significant designer productivity and design PPA challenges stemming from escalating constraints complexity. Customers can also expect to benefit from a more expanded feature roadmap of performance-optimized solutions down the road. In addition, a larger worldwide technical support team will be available to work with customers to help optimize constraints handling.
Q: How will design teams benefit from a unified constraints handling solution?
A: Designers will be able to enhance their chip design process by automatically generating and verifying golden timing constraints early in their design cycle. They will then be able to drive chip implementation with complete constraints that are formally proven to be correct and then manage the constraints as chip implementation progresses. As a result, design teams should experience improved chip timing, area and power, along with a shorter chip-implementation schedule with much fewer back-end timing closure iterations. Also, by formally proving the correctness of design constraints with a proprietary formal engine, designers can mitigate the risk of silicon failure resulting from incorrect timing exceptions.
Q: How exactly will the newly acquired timing constraints technology fit into Synopsys’ digital design flow?
A: FishTail’s approach has been to improve the chip design process by automatically generating and verifying golden timing constraints early in the design cycle. With its technology, we can take a large, complex RTL or gate-level design and automatically abstract the behavior and structure of the design, keeping only the information that’s needed for the task being performed. As a result, our solution can generate and verify timing exceptions on multi-million-gate designs in an overnight run with superior quality-of-results (meaning, no noise). The acquisition also brings us a solution that manages design constraints as chip implementation progresses. These capabilities complement the Synopsys PrimeTime® Suite, which provides a golden, trusted signoff solution for timing, signal integrity, power, and variation-aware analysis, and the Synopsys Fusion Compiler RTL-to-GDSII Solution, which enables a highly convergent, full-flow digital implementation along with the Synopsys Design Compiler® NXT RTL synthesis solution. The Design Compiler NXT solution provides fast, highly efficient optimization engines, cloud-ready distributed synthesis, and a highly accurate approach to RC estimation. Customers will be able to stay within our constraints handling environment, avoiding the tedious, error-prone, and manual multi-tool flows that are common in the market. All in all, Synopsys is excited to continue helping our customers achieve silicon success with a robust front-end, implementation, and signoff flow.