Synopsys & Georgia Tech Team Up on Reinforcement Learning-Driven Research—Win DAC 2023 Best Paper Award

Synopsys Editorial Staff

Jul 13, 2023 / 3 min read

For their innovative approach in applying reinforcement learning techniques to push the boundaries on power, performance, and area (PPA) in digital designs, a team of engineers from the Synopsys EDA Group in collaboration with Georgia Tech were honored today with the prestigious Design Automation Conference (DAC) Best Paper Award. Their paper, “RL-CCD: Concurrent Clock and Data Optimization Using Attention-Based Self-Supervised Reinforcement Learning,” was the culmination of six months of collaborative research into methods to drive concurrent clock and data-path (CCD) optimization in physical design.

State-of-the-art digital implementation tool flows use CCD to deliver the highest frequency and lowest power chips. Optimization and clock R&D experts in the Synopsys EDA Group have been working on the problem of datapath-aware CCD to achieve true concurrency in CCD for timing and power, which is a complex global problem with hard-to-model trade-offs between the clock and datapath. Based on the research done through this collaboration, RL-CCD emerged as a method to improve CCD quality by prioritizing endpoints for useful skew optimization using a self-supervised attention mechanism. The team’s experimental results on 18 industrial designs at 5nm to 12nm process technologies demonstrated that RL-CCD can deliver up to 64% better total negative slack (TNS) compared to the best-in-class production solution for CCD.

The Synopsys team involved in this effort include Wei-Ting Chan, a staff R&D engineer; Deyuan Guo, a sr. staff R&D engineer; Sudipto Kundu, a Synopsys scientist; and Vishal Khandelwal, a Synopsys scientist. The team collaborated with Dr. Yi-Chen Lu, then a Ph.D. student at Georgia Tech who interned at Synopsys over multiple summers, and Dr. Sung-Kyu Lim, a professor at the university’s School of Electrical and Computer Engineering and director of the school’s GTCAD (Georgia Tech Computer-Aided Design) Laboratory. 

deep reinforcement learning chip design tools

Sharing New Ideas to Tackle Chip Design Challenges

The Synopsys team notes that they are humbled and honored by the award; their paper was chosen from more than 1,000 submissions. They also appreciate the opportunity to collaborate with domain experts across clock and optimization teams and Georgia Tech. “Collaborating with universities is always beneficial, and research builds our core technology asset,” said Chan. “It’s very important to bring in stimulating ideas and try them on real-world problems.”

Kundu noted, “The academic and industry knowledge bases need to come together on pathfinding projects. Through six months of this collaboration, we persisted with new ideas and finally converged on RL through the process of innovation.”

Lu and Lim brought to the research project their knowledge and expertise in AI and machine learning (ML). During the course of his multiple Synopsys internships, Lu had the opportunity to work on many projects with Synopsys engineers; the RL-CCD project was the latest. Synopsys, too, brings strong AI expertise to the table. The company continues exploring how ML can help solve problems and on integrating AI into more of the chip design and verification flow through solutions such as the new™ full-stack, AI-driven EDA suite. Said Guo: “We explored various approaches to tackle this problem, and each has its own challenges. RL, while it does take a lot of run time, proved to be an effective approach for addressing the clock and datapath optimization challenge.”

“This work exemplifies the potential in taking real-world problems from industry and looking at them through the lens of new approaches with academia,” said Khandelwal. “We have been collaborating with Professor Lim and his student Yi-Chen for several years, as part of the Synopsys Academic & Research Alliances program, working on innovative solutions to many problems. Kudos to the team for getting this prestigious recognition!”

Nurturing the Next Generation of Semiconductor Engineering Talent

While there are more considerations and steps that need to happen before a solution under research becomes a product, the team hopes to duplicate their approach with future university collaborations. Indeed, working with and supporting academia is a key initiative at Synopsys. This focus is exemplified by the work of Synopsys Academic & Research Alliances (SARA). SARA, which showcased its programs at the 60th DAC event, builds bridges with universities around the world and supports student-focused efforts such as internships, helping to nurture the next generation of engineering talent. 

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