Collaboration for Innovation: How Synopsys and TSMC are Advancing Chip Design

Advanced nodes collaboration

• Enabling power and clock signals routing on the backside of the semiconductor wafer instead of traditional frontside approaches, we’ve been working with TSMC on the feature enablement for TSMC A16™ technology.
• Using Synopsys Foundation IP, we’re easing the transition from System-on-Chip (SoC) to the advanced 2nm process that is based on nanosheet transistor technology by tackling the inherent challenges of variability, parasitic extraction, and modeling accuracy.

Enabling multi-die designs

• Working in collaboration with TSMC and Ansys, we’re developing a holistic design process for integrating electronic and photonic components using TSMC’s Compact Universal Photonic Engine (COUPE) technology. The comprehensive process covers all stages of design, from initial concept to final implementation.
• We’re also working with TSMC and Ansys to solve multiphysics challenges in multi-die designs. This involves the use of our 3DIC Compiler and TSMC 3DFabric® technology to overcome thermal management, electromagnetic interference, signal integrity, and power integrity hurdles.
• We partnered with TSMC to demonstrate two dies communicating via the high-speed UCIe (Universal Chiplet Interconnect Express) specification. Our UCIe IP and Silicon Lifecycle Management products were at the heart of the demonstration, showing the speed, reliability, and health of the multi-die interconnect.

Using AI to accelerate design cycles

• With Synopsys.ai, we’re delivering production-ready, AI-driven EDA flows on TSMC N2 technology that speed up chip design cycles and quality of results. In addition, our 3DSO.ai solution provides AI-driven early exploration and analysis of multi-die designs.
• Our AI-enabled solutions can also adapt and optimize designs for TSMC technology platforms, reducing design cycles and accelerating time to market.