Virtual Prototyping: Fast, Accurate, and Standards-Based Approach

Synopsys Editorial Staff

Nov 10, 2016 / 1 min read

Introduction to Timing Models in System Simulations

In system design, accurate timing is essential. While software development often relies on abstract, loosely timed models for quick simulation, virtual prototypes for early performance analysis demand more precise timing. This necessity marks a significant shift from the high-level abstraction of SystemC TLM-2.0 LT (Loosely Timed) models to the detailed cycle-accurate RTL.

The Gap Between Loosely Timed and Cycle Accurate Models

Bridging the wide gap between these two extremes – from Loosely Timed to cycle-accurate models – might seem daunting. Fortunately, a middle ground exists, tailored for this exact purpose: the TLM-2.0 AT (Approximately Timed) modeling.

TLM-2.0 AT: Bridging the Accuracy Gap in Timing Models

TLM-2.0 AT offers a foundational protocol for modeling timed communication. However, its generic nature means it doesn't capture every feature of actual protocols used in production System on Chips (SoCs), thus limiting its accuracy for early performance analysis. The good news is that the TLM-2.0 standard includes extension mechanisms. These allow AT models to accurately represent popular industry protocols like AXI, enhancing timing precision while maintaining compatibility with AT models. The result? A powerful blend of speed and accuracy.

Comparing TLM-2.0 AT and Fast Timed AXI Extensions

Consider a simple system simulation to highlight the differences. In this scenario, both systems – one using the TLM-2.0 AT base protocol and the other employing Synopsys Fast Timed TLM-2.0 extensions for AXI – execute a mix of read and write operations. Despite both systems being speedy enough for architectural exploration, there’s a notable distinction in accuracy.

Hardware with FT AXI extensions

The Impact of Fast Timed AXI Extensions on Simulation Accuracy

The FT AXI system, with its detailed representation of the AXI protocol, shows more realistic behavior in throughput and transaction duration. Conversely, the system using only the TLM-2.0 AT base protocol, while optimistic, lacks crucial features like beat timing for burst accesses and concurrent read/write capabilities, leading to potential under-design risks.

Synopsys Platform Architect: Integrating Fast Timed Extensions

Synopsys Platform Architect simplifies integrating Fast Timed AXI Extensions into TLM APIs. This integration spares model creators from delving into protocol specifics, ensuring seamless interoperability between FT and AT models.


In summary, for early performance analysis in architecture modeling, the choice is clear. Fast Timed Extensions not only provide superior accuracy but also maintain speed and adhere to industry standards. By opting for these extensions, architects gain a realistic performance estimate, avoiding the pitfalls of under-designing. Fast, accurate, and standards-compliant, Fast Timed Extensions are the go-to solution for bridging the accuracy gap in timing models.

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