ESP Equivalence Checking in Custom Design: An Interview with Almitra Pradhan

Q: Hi Almitra! Thank you for taking time with us today to talk about equivalence checking for custom designs. Let’s start with ESP’s technology. How does it help custom designers catch bugs in their design?

Almitra Pradhan

ESP’s symbolic simulation engine is very efficient in verifying embedded and compiled memories, standard cells, and IOs. With this technology, users can run a few automatically generated symbolic vectors to cover the design space saving them runtime and incomplete coverage issues from binary vector-based verification. Our customers use ESP for signing off memories for functional correctness before taping out.

Q: What are the most common applications for ESP and what is the most significant value it brings to customers?

Almitra Pradhan

ESP is most commonly used for verifying SRAMs, register files and TCAMs. The most significant value that ESP brings to our customers is the ability to uncover corner case bugs in the design. With a traditional binary vector-based testing methodology there can be test escapes when a vector exercising a particular scenario is not generated. This can lead to functional failure of a chip due to an untested scenario - something that any designer wants to avoid. As ESP needs only a few symbolic vectors that ESP’s testbench automatically generates, this is a huge advantage for applications such as memories in providing full coverage verification.

Q: Beyond memories, what are the other common applications where ESP could be used?

Almitra Pradhan

ESP’s library verification capability is very useful for customers who are testing standard cell libraries. Especially for complex sequential cells, the symbolic verification capability again shines in catching various corner case conditions. Most often this leads customers to correct their reference models or design implementation based on the design bugs ESP can catch.

Q: Does ESP verify the custom designs directly at the transistor level?

Almitra Pradhan

Yes, ESP verifies the netlists at the transistor level - we do not need users to abstract or topologically identify any circuit types. This greatly simplifies ESP’s setup for the user. ESP is highly flexible in its ability to support all design specifications such as Verilog (behavioral, RTL, gates, or switch level), SPICE, compiled Liberty (DB) files and you can mix and match i.e. Verilog to SPICE, Verilog to Verilog, Verilog to DB, DB2DB, etc.

Q: You mention ESP offers much more than functional verification. Can you elaborate more on that?

Almitra Pradhan

In recent years we have introduced several added solutions over and above the base equivalence check capability. Some of the features that customers find very useful are power integrity verification, redundancy scheme verification, scan chain verification, and SPICE memory bitcell bitmap generation. These are unique capabilities possible with ESP’s technology.

With power integrity verification, ESP can dynamically find power-consuming shorts, incorrect isolation in powered down domains, or missing level shifters in multi-voltage domains. With our redundancy verification capability, users can verify if the row/column memory redundancy scheme is working as expected for the designed fault tolerance and generate the repair table for their redundancy scheme. The scan verification capability helps verify the scan chain order while the Logical2SPICE solution helps users map the bitcell locations hierarchically to the netlist instantiations.

Q. That sounds very interesting, what are the future directions of the product?

Almitra Pradhan

In ESP we are currently working on expanding our offering in the IO verification space. We are also working on verification solutions for new and upcoming memory technologies such as MRAMs. And while new offerings and solutions are underway, we also continue to further improve our capabilities to address challenging issues in the verification of memories such as complex multiport memories, sleep modes, and power-up design methodologies.

ESP’s continued objective is to enable custom designers and verification engineers to catch any design bug easily in their increasingly complex designs.

Q. Almitra, thank you so much for giving our readers an overview of ESP and its value in the verification of custom design and memories.

Almitra Pradhan

You are welcome! Thanks for having me.