256Gb/s Ready Set Go: PCIe Gen6 Verification IP

Let’s look at some of the vectors driving the need for PCIe Gen6 standard and achieve increased bandwidth and I/O performance. According to PCI-SIG, I/O Bandwidth doubles every three years and PCI Express protocol is the key enabler for designing higher capacity systems generations after generations.

Emerging applications such as AI, ML, and Autonomous driving are immensely data intensive. Application performance and quality of results critically depends on the richness of data and performance of the compute infrastructure. PCIe Gen6 provides a scalable speed upgrade to meet higher data throughput requirements of these heavy workloads processed by specialized CPUs and GPUs efficiently.

In addition, ever increasing performance requirements drives different approaches such as edge and distributed computing. PCIe Gen6 and other PCI Express based high performance interconnect standards such as CXL enables design of distributed and interconnected systems that are scalable. While PCIe Gen6 is the most significant and disruptive update in the last decade, it remains backward compatible therefore enables building the new infrastructure incrementally and in a cost-effective manner.

There are server storage technologies which utilize PCI Express extensively. High I/O throughput storage such as NVMe and SSD devices virtually localize the data for HPC nodes by making it accessible at an instant and maintain streaming rates with the help of PCI Express and Ethernet protocols. Hence speed boost provided by PCIe will significantly improve the functionality in the overall infrastructure. The disruptive nature of PCIe Gen6 specification will create new verification challenges for NVMe, SSD and other PCIe based storage technologies. Synopsys PCIe Gen6 VIP and Source Code Test Suite will help you address these challenges successfully.

4 signal levels of PAM4 helps transmit twice as much data as NRZ without having to double the transmission bandwidth for PCIe 6.0

Why Forward Error Correction (FEC)?

PAM4 signal is fragile by nature which would be compensated by using Forward Error Correction methodology. This is introduced by keeping in mind that data integrity is critical. Hence constant stream of error correction data will be supplied to make sure we do not lose time in re-transmitting the data. It will ensure low latency and bandwidth efficiency.