Design planning is the process by which you manage and minimize engineering tradeoffs related to implementation and design closure. Structural and architectural choices must be made during this stage. Because of the increase in design complexity and time-to-market demands, these strategic choices must be made as early as possible. Handling dirty or partial data is a key component in a leading design planning flow. Teams must be able to quickly assess and reassess early design choices to eliminate costly loops.

What Are the Challenges Associate with Design Planning?

The move to advanced nodes is forcing designers to pack more and more devices into smaller geometries. The challenges of managing design capacity at these advanced nodes are growing. The massive growth in both logical and physical complexity are just the beginning. The new process nodes bring demanding increases in manufacturing variability. Power management has also grown as a focus to ensure functional longevity for devices with stringent thermal design points. Designers who must make judgements about block area, connectivity, or dataflow can be challenged in creating unfeasible implementation ‘solutions.’. Shrinking time- to- markets have a significant impact on designers’ ability to meet these challenges with high- quality of results (QoR).

More devices, more variability, more corners and modes, more focus on managing power, and more need for design re-use are making design planning a critical component in chip development.

How Do You Perform Design Planning?

There is no one-size-fits-all approach for design planning. Every design and even every revision of a design will potentially need to tap into varying facets of the design planning toolbox. It is imperative that this toolbox is not only comprehensive in its scope but also each of the tools within it delivers optimal and convergent results. Useful attributes in this toolbox include:

  • Capacity to handle the largest design optimally yet seamlessly
  • The speed to do this efficiently while, most importantly, delivering leading (QoR)
  • Leading methodologies to enable any design style in the most efficient way possible

QoR will always increase if the tool is able to see across all user-defined logical hierarchy coupled with the intended associated physical hierarchy. Ensuring that this information is available at the relevant points in the planning flow can ensure that the design will ultimately converge.

Synopsys IC Compiler™ II provides a data model that delivers fast access to data for the applications that layer upon it. It provides significant increase in capacity to implementation and optimization tools without imposing inefficient abstraction. The library and design data are combined into a single data structure, removing redundancy to provide a compact representation of underlying data.

Synopsys IC Compiler II automatically and intelligently creates outline models of logical hierarchy during netlist consumption. Users can dramatically reduce memory requirements while enabling accurate and fast, top-level exploration and planning. All logical hierarchy is maintained without the need to flatten or manually uniquify the design, ensuring continuance of well-known testing methodologies while freeing users from complex hierarchy management. This high-capacity methodology provides scalability for design exploration while minimizing runtime and memory.

Turnaround time (TAT) during design planning is much more than tool optimization. There are numerous aspects that need to be understood and managed to begin to converge on a design that will close when bringing everything together. Design planning requires knowledge of many varying tasks to deliver an optimal floorplan.

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