Synopsys Protocol Verification Solution for UCIe 1.0

Need for Multi-die Chiplets Interconnect

Key applications like cloud, AI, 5G, automotive, and high-performance computing (HPC) coupled with the rapidly changing physics and economics of semiconductor scaling are leading to diverse integration trends and new die-to-die use cases. Semiconductor chiplet packaging (multi-die) is helping integrators take a new approach to build scalable and modular designs.
Multi-die SoC architectures are enabling bigger, more powerful SoCs than can be achieved with monolithic designs and at a lower price point. It also enables better scalability and composability of products leading to faster time to market and higher flexibility to address multiple market segments. Die-to-die interfaces are a key enabler of the multi-die SoC trend. Die-to-die interface needs to provide a seamless interconnect between dies with the lowest latency and highest energy efficiency in order not to impact system performance.

UCIe Chiplet Standard

In March 2022 the newly formed Universal Chiplet Interconnect Express (UCIe®) organization announced the ratification of the UCIe specification. Synopsys is a contributing member of the UCIe organization bringing a unique perspective to the industry consortium as an industry leader for EDA and IP solutions.
UCIe covers the complete protocol stack as well as the physical layers so it can address the most relevant multi-die SoC use cases. In contrast, other standard efforts have mostly focused on the physical layer aspects of the interface. The UCIe specification is compelling for the performance metrics it proposes as measured by edge efficiency, power efficiency, and latency, which will play a major role in driving the adoption of standards. The following are the key protocol features of UCIe 1.0 from a chiplet interconnect standard perspective:

• Protocol layer definition for non-coherent and coherent die-to-die links
  • Implements FLIT (flow control unit) to transport PCI Express® (PCIe®) and Compute Express Link (CXL) traffic over UCIe, and to be able to extend the existing software ecosystem
  • Streaming mode with vendor-defined FLITs for custom protocols
• A first-of-its-kind signaling interface between different layers of the protocol
  • FLIT aware die-to-die interface (FDI)
  • Raw data die-to-die interface (RDI)
• Physical interconnect signaling interface with usage models for single module and multi-module
  • Data rates up to 32 GT/s
  • Standard package (x16 lanes) and advanced package (x64 lanes) with a channel reach of 25mm/2 mm
  • Transfer mode as a serial with clock shared between chiplets
  • Degraded width/rates of operation
  • The main band interface for data path, sideband interface for control and bringing up
  • Lane repair and Lane reversal features
• Larger channel lengths through UCIe Retimers

Unlike most of the other standards, UCIe provides software stacking along with the physical layer to realize key functional parameters. The figure below provides an overview of the UCIe stack and functional aspects at each layer.

Following are the key verification aspects and challenges seen when verifying a multi-protocol, multi-stack, and multi-module DUT type:

• Device capability discovery and configuration settings of the DUT to match upstream port capabilities using sideband interfaces
• RDI, FDI, vLSM and link-state machines and transitions
• Assessment of retry mechanism behavior at the die-to-die layer
• Training, lane reversal, and lane repair features at UCIe physical layer
• Effective way of generating protocol layer traffic based on discovered capabilities
• Ensuring reliable traffic for PCIe/CXL raw modes or UCIe defined FLIT modes including integrity and data encryption by protocol layer
• End-to-end data integrity for custom protocols defined over the streaming mode of operation
• Overall protocol performance throughput based on physical layer lane width and whether data rate capabilities are meeting design expectations