How to Design SoCs for the SysMoore Era

Dr. Ming Zhang

Feb 16, 2022 / 6 min read

To use a surfing analogy, Moore’s law has been a mighty long wave. But as any experienced rider knows, no wave is infinite. The complexity that it has encouraged has ultimately slowed it down. This is no bad thing, however: the new era we find ourselves in — the SysMoore era — offers unprecedented opportunity for innovation.

Today, we look at innovation as the single unstoppable feature of the semiconductor industry. We are concurrently confronting challenges such as the global shortage of semiconductors, a global pandemic stimulating electronics usage, and our ever-lasting desire to create smarter hardware for more diverse applications, faster. This new world of innovation, defined by scale and systemic complexity, depends on the intersection of chips and software to fuel a fundamental shift in product development. As scaling a single chip has become more difficult, teams have had to adapt to maintain the exponential growth that they are accustomed to. However, the complete landscape is far bigger and presents an opportunity for higher impact.

What’s behind it? “SysMoore,” a term that our co-CEO and chairman Aart de Geus coined in 2021, refers to a new design paradigm that fuses Moore’s law with innovations built on systemic complexity.

Read on to learn about what’s driving the surge in systems-of-chips (SoCs), SoC design creation for the SysMoore era, EDA as an innovation catalyst, and opportunities that lie ahead.

Person with glove holding a chip

Key Manufacturing Trends Shaping the Chip Design Industry

For half a century, logic and memory scaling have largely driven the semiconductor industry’s development. That is now changing as three-dimensional interconnects enable scaling beyond the miniaturization barrier. More than ever, the design and manufacturing of chips and packaging need to work hand-in-hand, regardless of whether they’re organic substrates or silicon interposers.

From everyday gadgets to self-driving cars and large IT systems, the need for parallelized computing systems and high-performance chips that can push existing power, performance, and area (PPA) limits demand disruptive innovations in chip design solutions, from silicon to software.

While this means that chip design and manufacturing are becoming more complex processes, it also signals more opportunity for innovation given the sheer range of technologies that SoC designers now have at their disposal.

A New World of Innovation: System-of-Chips and Hyper-Convergent Designs

Simply put, we are seeing a ground-breaking shift in product development, in terms of materials, design, and possibilities. The future of “Smart Everything” requires industry-changing evolution and innovation to be compressed into periods of years or months as opposed to decades.

Today’s transistors are three-dimensional and work in conjunction with one another. In Gordon Moore’s world, performance, power consumption, and signal integrity could be addressed independently. With the wide demand for AI across markets, the amount of memory that’s available for AI training has doubled every year while the model size increased by about 100 times. We are now seeing a shift from designs based on massive single chips to multiple pieces of silicon integrated into a single package via 2.5D or 3D designs. This evolution, in the context of SoCs, has transformed the humble SoC from “system-on-chip” to “system-of-chips.”

SysMoore vs. Moore's Law

System-of-chips is a solution with three main ingredients: the known good dies (KGDs), which we can think of as building blocks; the interconnects that join them together; and the system as a whole. Autonomous AI tools support everything from the initial definition, design implementation, to manufacturing. They also enable testing and in-field optimization, which are critical to successful deployment of the final product. Networking SoCs, switches, or co-packaged optics modules lend themselves to integration because their underlying ingredients originate from different process nodes, and it makes sense to combine their strengths.

In the context of the SysMoore era, hyper-convergent designs represent a new class of semiconductors that integrate multiple technologies, multiple protocols, and multiple architectures into one massive, highly complex, and interdependent design.

However, this shift to hyperconvergence has uphill implications for chip designers. Combining numerous technologies into a single system calls for a corresponding shift in mindset from one of singular focus to one that is more holistically analytical. Applying this effectively results in a hyper-convergent design flow where the front-end process considers the impact of back-end effects. Failing to do this in the SysMoore era means a cumbersome, costly back-and-forth and delayed market delivery.

Data is central to this new way of operating. All tools in the hyper-convergent design flow share the same data model, which enables seamless sharing of front-end and back-end information throughout the various phases of the design process.

EDA as an Innovation Catalyst

With the enormous amounts of data being generated, electronic design automation (EDA) is becoming indispensable for both designers and manufacturers as they transition from working in two dimensions to three. While Moore’s law enabled AI to come to fruition, the demand for AI across almost every industry is now such that the semiconductor sector must reckon with a level of design complexity beyond human engineering and economic capacity.

The EDA industry offers the software and hardware to make otherwise impossibly advanced semiconductors. With the right “secret sauce,” these solutions can now perform simultaneous analysis of hyper-convergent designs across all the dimensions of interest. The key is ensuring that these solutions and the design flow are orchestrated to analyze hyper-convergent designs. At Synopsys, we have addressed this additional logistical challenge with Synopsys 3DIC Compiler,

the industry’s only unified, 2.5D and 3D multi-die package co-design and analysis platform. Built on the common, single-data-model infrastructure of the Synopsys Fusion Design Platform™, 3DIC Compiler coalesces numerous transformative, multi-die design capabilities to offer a complete architecture-to-signoff platform – all in a unique, consolidated user environment.

Last year, de Geus sat down with some of the top journalists at The New York Times, Forbes, and Anandtech to discuss the advanced innovation that is required to overcome these obstacles and push the semiconductor industry forward.

“With classic Moore’s law, we saw an unbelievable push in scale complexity that finally made AI possible. Now every vertical market seeks to extract economic value from their data by making everything smart. This has created a pull on the semiconductor industry to deliver another 1000x to tackle the systemic complexity that ‘smart everything’ creates. But 1000x means overcoming levels of design complexity that far exceed human engineering capability and economic means today,”  de Geus said in a conversation with Marco Chiappetta of Forbes.

The Future of Possibilities

High-profile silicon design teams are already using tools like Synopsys, the world’s first autonomous AI tool set for chip design, to accelerate time to market with a better semiconductor placement than human designers can achieve.

At Synopsys, we also use cell-aware design-for-testing (DFT) to ensure the highest possible quality for KGDs, factoring in speed, temperature, and power. We support static and transition testing for TSV or RDL interconnects, and built-in self-tests for physical layer (PHY) interconnects. Broken wires are inevitable given the high-speed nature of the design process, so it is essential to be able to detect and repair defects equally quickly.

Being able to compare data from the initial design phase with testing results means better design, faster performance, and lower power expenditure. In the production phase, the ability to correlate data with test results on an entire chip means you can identify any outliers and raise the overall quality of the final product.

As we enter the age of autonomous driving, factors like in-field optimization will feed a vehicle with the data it needs to perform at its best, with top-level security. In the SysMoore era, the complexity inherent in the new breed of SoCs means lifecycle management becomes more important than ever.


To ensure that this new world of innovation sees progress as it should, we need to come together as an industry. Picture, for example, assembly design kits comprising mechanical, electrical, photonic, and thermal properties enabling system-level co-design. Or a common industry standard to ensure supply chain security. Again, the nature of the advanced packaging we are now seeing will make inline process control a necessity. All of this depends on data exchanged with trust between multiple parties, from vendors to system OEMs.

AI technology has made the SysMoore era possible, allowing us to create more chips and higher performing systems while minimizing the use of time and resources. Now it is up to us to realize its true potential, by giving innovators wings.

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