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The future of computing depends on miniaturization, and extreme ultraviolet lithography (EUV) is one key enabler. Until recently, we have relied on low numerical aperture (NA) EUV systems with an aperture of 0.33 to help us reduce the size of integrated circuits (ICs). As with deep ultraviolet (DUV) technology, this has begun to reach its limits. High NA EUV lithography with a 0.55 aperture represents the next phase for chip production.
Advanced logic device manufacturers are already carrying out modeling and simulation work based on this emergent technology due to its multiple benefits, including higher resolution. However, as you might expect, this technology is changing the chip production ecosystem and brings with it new challenges. Implementing High NA EUV effectively calls for corresponding computational support to enable more advanced modeling.
The Challenges of High NA EUV Lithography
Some of the biggest hurdles that this technology presents relate to new materials, new mask structure and modeling, new imaging technology, and the stitching together of exposure fields.
Firstly, let’s consider anamorphic imaging. In a High NA EUV projection system, the reticle reduction factor remains at four times horizontally but increases to eight times vertically. This means that the mask correction strategy must be adjusted individually for both directions. This also reduces the available field size by half, requiring designs to be split between two reticles and stitched together. This makes it necessary to factor anamorphic conditions into design and mask rules.
Aberration sensitivity also becomes more important. Aberrations are the result of optical imperfections that cause variation in the projected pattern. This can affect critical feature dimensions, contrast, and placement. To remedy this, accurate modeling of aberrations will be a critical part of predictive lithography simulations.
Next, High NA EUV changes the makeup requirements of the mask, which is composed of an absorber and multilayer reflector. Designing masks compatible with High NA EUV technology means balancing factors such as pattern fidelity, reflectivity, and process compatibility. Uniform reflectivity is difficult to achieve, and aspects such as material properties, interface roughness, and process variations all affect performance. Advanced computational techniques such as reliable electromagnetic simulations and optimization algorithms will be essential to the design and manufacturing processes.
Finally, electromagnetic effects are a further consideration that apply to both Low and High NA EUV technology. While High NA EUV doesn’t cause an increase in electromagnetic effects, it does call for a higher level of accuracy to model those effects along with increased complexity due to asymmetry on the photomask used in the chip production process.
Computational Lithography Breakthroughs
To overcome these issues and make High NA EUV a reality, computational lithography solutions must be employed. Synopsys has taken important steps in this area to enable more rigorous simulations, predictive compact modeling, source mask optimization (SMO), and inverse lithography (ILT).
In terms of modeling, we must make an important distinction between accuracy and predictivity. This means not just being able to describe what is on a wafer, but to predict how it will react in different situations, calling for a physical model (which rigorous simulation can provide).
Rigorous simulation is used to predict the imaging performance of High NA EUV systems, helping designers and manufacturers understand resolution limits, process windows, and contrast characteristics, as well as optimizing the lithography system. Specific applications include mask design and source optimization.
Synopsys S-Litho sets the bar for lithography simulation in semiconductor process development and optimization in advanced memory and logic applications. It offers a foundation for all necessary simulations in the context of High NA EUV. Its unique capabilities cover anamorphic imaging, aberration classification, understanding novel resist materials, mask scale representation, and the generation of new source shapes.
The nature of High NA EUV means there is a wider range of variation in the lithography process. Images formed from the mask through EUV are subject to effects such as flare, shadowing, and mask stack reflectivity. Engineers must optimize the reflective mask substrate and EUV-specific mask absorber stack to manage this variation. This is achievable through a combination of simulation and compact modeling. To cater to this need, Synopsys offers advanced compact 3D mask modeling through Synopsys Proteus applications that matches a rigorous model reference through a series of patterns factoring in critical dimension, focus, and slit position.
The advent of High NA EUV also means that SMO must reckon with anamorphic and central obscuration effects. Synopsys Proteus has the advantage of being able to export the source and mask solution to S-Litho for rigorous testing, helping to realistically assess the performance of the final source.
Lastly, the scope of the application of inverse ILT has expanded. High computational costs and the curvilinear nature of its mask layouts made fabrication challenging which is compounded by the expansion of ILT to full-chip processing. With recent computational breakthroughs, we are now well on the path of using ILT in full-chip manufacturing for both memory and logic chips.
Furthermore, multi-beam mask writers have made masks with curvilinear features applicable to high-volume manufacturing. These masks provide the highest fidelity lithographic performance and will significantly contribute to the adoption of High NA EUV as well as the extension of Low NA EUV. ILT provides greater degrees of correction freedom as well as native support for curvilinear masks which are less impacted by mask rule constraints. It is ideally suited to dense designs where there is little room for proximity corrections. Synopsys Proteus ILT delivers high-fidelity curvilinear proximity correction with full mask rule compliance, offering a much-needed correction solution.
While High NA EUV lithography does present major challenges, the right SMO and ILT tools enable designers to be ready to embrace this important and necessary development in IC innovation.
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