Accelerating Networking SoC Design with Cloud Emulation

Dr. Johannes Stahl

Jun 16, 2021 / 5 min read

The exigency of increasing functionality required from today’s networking chips is no secret.

The semiconductor industry is witnessing an increasing demand in fueling fast-growing application areas such as high-performance computing (HPC), 5G, GPU, artificial intelligence (AI), and automotive. As such, the requirements for today’s silicon to sustain high bandwidth and low latency become the need of the hour.

While networking system-on-chip (SoC) design continues to be a key area of focus for the electronic design automation (EDA) industry, design delivery cycles and time-to-market windows have dramatically shrunk. In parallel, the rise in data, network traffic, and demanding software protocols impel an increase in design size and port density to satisfy demands, adding to a ripple effect of network complexities. Simply put, chipmakers remain under pressure to do more in less time. Despite the gradual slowing of Moore’s law and adoption of new process nodes, the demand for larger throughput and lower latency is unlikely to ebb.

To accelerate networking SoC readiness across both hardware and software domains, design and verification teams need to be equipped with the right tools and infrastructure to locate and fix problems early in the design cycle before they become costly and hard to resolve.

From effective power analysis at the gate level to timely addressal of network performance needs, sophisticated verification methods are even more critical; the use of emulation to evaluate full-chip functionality takes on an even more vital role for making the most advanced chips successful.

Read on to learn more about how design and verification of networking SoCs has evolved over time and why a shift toward cloud-based emulation addresses the gap to accelerate next-gen innovation.

Achieving Breakthrough Verification Efficiency with Cloud-Based Emulation

Keeping Up with the Evolving Networking SoC Industry

For any network, a crucial component that governs its overall functionality is its routing strategy. Efficient routing has become critical in today’s increasingly complex network structure and allows for the transfer of internet protocol (IP) packets from one point to another. Finding the fastest and most effective data path between nodes becomes crucial. Today’s networking SoCs are a lot more complex than they used to be.

Firstly, the success of the design is heavily reliant on solving two complexity vectors — hardware and software. The more ports embedded on the chip — anywhere from 64 to 128 to 512 — the more ethernet streams come to play. This results in the need for robust network traffic management and accurate routing strategies to ensure ethernet packets are routed through the silicon and reach their destinations in a timely manner. Secondly, the larger the chip, the more software flexibility is embedded. This makes verification more complex because of the various network and logic paths that need to be exercised.

Why the push toward more software? With the emergence of software-defined networking (SDN), teams can now control traffic centrally and dynamically. Chips now mimic data paths with complex control logic, while intelligence is moved to software for better health and monitoring capabilities, in addition to increased functionality and automation. These software-backed networking chips are then used to fuel a wide array of applications, from supporting navigation systems in automobiles to powering network infrastructure in 5G.

Emulation is key to verifying networking SoCs and using real-world network scenarios.

Today, in a standard pre- to post-silicon cycle, it takes an average of 10,000 emulation runs to successfully complete the full-chip pre-silicon testing process. These are time-consuming emulations that are executed during multiple iterations over a day and take anywhere between hours to days on large designs with realistic workloads. Semiconductor companies need to leverage state-of-the-art emulation techniques that deliver optimized performance and turnaround time to conquer such needs.

The need for fast emulation becomes essential.

This is not only an ideal approach for running more cycles in less time but also gives customers more bang for their buck. This can be augmented by parallelism to leverage parallel SoC model runs on the emulator and optimize end-to-end performance.

Cloud-Based Emulation: The Superpower to Accelerate Chip Innovation

Fast emulation with flexible resource availability allows design teams to perform accurate verification earlier in the design cycle, so they can minimize the risks of missed SoC efficiency goals and battle network congestion and outages.

Efficiency for, say, a 5-billion-gate emulation capacity means that all the emulation capacity available through its lifecycle should be active 24/7. Throughout this networking chip lifecycle, the design processes change based on projects that require different design sizes to run on the system. In the traditional method, a physical tester would need to be set up for every single piece of design and run for multiple weeks before reconfiguration can begin. With virtualization, reconfigurations happen (software controlled in an instant), allows for ultimate flexibility, and maximizes the validation of realistic network traffic scenarios with 2x more efficiency and effectiveness than with the classic in-circuit approach.

By providing emulation access on the cloud, teams now not only have access to emulation from anywhere in the world 24/7, but also do not need to spend the effort to house an emulation system on-site.

That is why there is a need for a reliable, flexible, and secure solution that satisfies market emulation requirements without the need to build individual data centers, while adding capacity for specific use cases to verify multi-billion-gate chips. As cloud services continue to take design, storage, and security to new heights, enterprises need a reliable and high-performance solution that leverages the power of the cloud to accomplish system-level verification tasks faster.

Enabling Next-Generation Emulation with ZeBu Cloud

Part of the Synopsys Verification Continuum™ Platform, ZeBu® Cloud delivers the performance needed to make verification teams and software developers working on the most advanced chips successful. The Synopsys Verification Continuum is not only a platform for all verification solutions, but also exploits the commonalities between different verification technologies with front-end compile, debugging, and interface protocols.

Unmatched by any other emulation cloud solution in the market, ZeBu Cloud provides the industry’s highest emulation performance. This comprehensive, one-stop hosted emulation solution delivers on-demand, turn-key, and secure emulation for the high capacity required by IP and SoCs. With no prerequisites of building or operating an emulation data center from scratch, ZeBu systems can run on the cloud and add capacity as and when needed. This way, design teams can collaborate with customers — pre-silicon — in a secure environment with the highest grade of data encryption.

ZeBu Cloud Diagram | Synopsys

At Synopsys, we leverage our leadership in the interface IP solutions market for our design and verification technologies —backbones that help us fulfill even the most distinct use cases. Our customers enjoy the fact that they receive the fastest performance from ZeBu Cloud, but they can also reap the benefits of building parallel instances of their designs to beat schedules with a cloud-ready approach.

Electronics companies will continue to invest in fast emulation and prototyping farms to accelerate software bring-up, performance validation, power analysis, or system validation for IP and SoCs. Based on this, we believe in relentless innovation and supporting customers with next-generation technologies to enhance the superpower of emulation and achieve maximum performance for networking SoC designs.

What’s Next in the World of Emulation?

As we enter a time where it is impossible to sign-off on a design without its going through exhaustive emulation, we expect chip designers to continue to push the limits of verification beyond anything we have even seen in the past. While general-purpose emulation will continue to grow, we anticipate a transition to application-specific emulation, driven by mission-critical use cases.

Chips will continue to evolve in an industry that is heavily dependent on the need for speed. Innovations in emulation will likely be the only path toward mastering the complexity of future networking SoC designs.

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