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VC Verification IP for USB4
Synopsys® VC Verification IP for USB4 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of USB4 based designs.
Highlights
- Native SystemVerilog/UVM
- Source code test suite (Optional)
- Built-in protocol checks
- Verification plan and coverage
- Debug using packet tracing
- Extensive error injection
- Runs on all major simulators
Key Features
- Imports existing USB3, PCIe, DP SVT VIP to run over USB4 Subsystem
- Enables reuse of USB3, PCIe and DP Test Suite tests over USB4
- Supports all router QoS (flow control) modes with QoS statistics
- Supports configurable number of adapters and paths per router
- Support credit aggregation for credit grant packets
- Supports host adapter interface multiple rings with raw/ frame mode
- Supports legacy mode (TBT3)
- Supports USB4 Retimer
- Supports simple configuration APIs to setup a complex subsystem topology over multiple tiers
- Supports TMU
- Supports full configuration space with backdoor access