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Synopsys Verification IP (VIP) for Ethernet 10/100/1000M and 10/25/40/50/100/200/400/800G/1600G (1.6T) provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Ethernet based designs.
Highlights
- Native SystemVerilog/UVM
- Source code test suite including UNH-IOL (optional)
- Runs natively on major simulators
- Built-in protocol checks
- Verification plan and coverage
- Verdi® Protocol Analyzer
- Trace file support for debugging
- Extensive error injection
Key Features
- Ethernet from 10M up to 1.6T
- IEEE 802.3-2022
- IEEE P802.3bs (200/400G Base-R)
- IEEE P802.3ck (100/200/400G)
- IEEE 802.3cd 100G RS-FEC (with optional FEC states), 50G Base-R, PAM4 Encoding
- BaseT/BaseT1 (1000BaseT, 100/1000 BaseT1, 10BaseT1S, PLCA, 10BaseT1S Transceiver)
- Auto-Negotiation on twisted pair (clause-28)
- IEEE 802.3by, CD & ETC specifications (25/50G)
- Consortium 800G, 1.6T IEEE P802.3dj draft
- AVB TSN specifications and drafts
- IEEE802.3cb (2.5G Base-X & 5G Base-R)
- IEEE 802.1AE (MACSec)
- SGMII, QSGMII, OSGMII, USGMII, USXGMII
- Flex Ethernet (OIF-FLEXE)
- Energy Efficient Ethernet (EEE)
- Auto-adaptation & Auto-negotiation
- MDIO clause 22 and clause 45
- Dynamic speed switching
- Custom header and payload insertion
- Debug port
MAC and PHY Interfaces
| MAC (Media Access Control) | PHY (Physical Layer) |
| MII, RMII, SMII, GMII, RGMII, SGMII, XGMII, XLGMII, CGMII, CDMII, DCCCMII/MDCMII MAC interfaces | TBI, XFBI, XSBI, XXVSBI, XLSBI, LSBI, CSBI, XLAUI, CAUI, CCXBI, CDXBI, DCCCXBI, MDCXBI and Base-T interfaces |
| AVB/TSN: Supports Frame Preemption, AVB 1722 Data & Control Frames, credit-based shaper | PAM3/4 encoding for applicable interfaces |
| Transmit and receive of multiple packet types in layers 2/3/4/7 | Forward error correction, auto-adaptation, auto-negotiation, and Reed Solomon Forward error correction for applicable interfaces |
| Generates and receives MAC Data, Control, PPP, PTP 1588, VLAN, SVLAN, JUMBO FRAMES | Skew insertion and lane reversal |
| GCM-AES-XPN-128/192/256 MACsec authentication/encryption | Base T, Base-X, Base-R, Base KR encoding/decoding |
| Send any legal or error injected packet | Auto-adaptation, auto-negotiation and FEC |
| Customize any field in a packet or between packets to a specific value | SGMII, QSGMII, USGMII, USXGMII |
| Send raw user defined packets | Simple, Flexible Control to modify any outgoing Codegroups/Codewords |
| Inject error in any field of a packet or between packets | Support Flex E 2.1, programmable number of Flex E Client/PHY, slot programming, overhead timer |
| Add multiple errors in a packet | Force loss of synchronization, mimic cable pull scenario |
| Low power idles (EEE) | Inject error in any field of a packet, Lower-level transactions to enable error injection at any PCS level |
| Send any legal or error injected packet | Callbacks at 66bit encoded /scrambled level, at transcoder level in transmitter, receiver and monitor for manipulation of data stream for Base-R interfaces |
| Customize any field in a packet or between packets to a specific value | Clock Data Recovery (CDR) |
| Configurable parallel interface width for PCS interfaces |
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| Configurable LPI, Align, Auto -Negotiation, Auto Adaption, Hi SER, BER timers |