Date: Thursday, June 20, 2024 

Time: 8:30 a.m. - 11:30 a.m. PDT / 3:30 p.m. - 6:30 p.m. UTC

Location: Virtual workshop with hands-on labs. This workshop is best suited for attendees based in North America and Western Europe. 

Login details will be emailed to all registrants. 

Do you want to harness the force of formal verification to ensure your mission-critical designs are ready for takeoff? Then join us for this virtual workshop!

In this 3-hour workshop, attendees will experience:

  • Running simple formal checks or exploring functional behavior to find bugs early - no testbench, no SVA, and no formal knowledge required
  • Engage in hands-on labs to find dead code, FSM deadlock, initialization issues, X-propagation, protocol violations, explore design behavior and find bugs early
  • See a demo on how Generative AI can assist you in becoming even more productive with formal verification and RTL development

This workshop will be presented by Synopsys formal experts. Attendees will gain hands-on experience in live labs and walk away with the confidence to use these functionalities in current and upcoming projects.

Workshop Agenda

*Subject to change

30 min

Welcome/introduction + review designer tasks, challenges and how formal verification can help

30 min

Deadcode analysis, FSM livelock and deadlock checks using automatic formal checks

30 min

Instructor-led hands-on lab #1

15 min


15 min

X-propagation checking

15 min

Verifying standard protocol interfaces

30 min

Formal design exploration and instructor-led hands-on lab #2

10 min

Generative AI demos

5 min

Wrap-up + Q&A

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Registration for this workshop is now closed.

Questions? Contact us