Tutorial - Streamlining Low-Power Verification: From UPF To Signoff

Presenters: Godwin Maben (Synopsys), Santhana Krishnan Kaliya Perumal (Meta), Neeraj Mishra (Google), Satya Ayyagari (Intel), Sean O’Donohue (Synopsys), Tushar Parikh (Synopsys)

Date & Time: Monday, March 4 – 1:30pm - 5:00pm (30 min break at 3pm) / Room: Oak

Abstract: 

Generative AI created a lot of interest recently and is poised to change our lives in many unimaginable ways. One significant change we already know is the huge amount of power it consumes: an AI chip with the functionality of GPT-3 and 175 billion parameters would require an estimated 1280 megawatt-hours, which is equivalent to about 120 gasoline-powered cars operating for one year and creating around 550 tons carbon emissions. ​

Generative AI and other similar applications leverage semiconductor devices, so it is imperative that such devices consume as little power as possible.  The most common power saving schemes are clock gating, separating power domains and voltage islands, installing retention cells, and designing efficient power management units.​

These low-power instruments add circuitry to the design and potentially impact design behavior. Verifying the functional intent of the design in the presence of the low-power constructs is critical. Low-power signoff is a new verification requirement for the chip design and verification community. ​

Just as functional verification and signoff requires different techniques, such as static, formal, simulation, and hardware prototyping to ensure design integrity, the same is true for functional verification of low-power designs. ​

This tutorial offers a comprehensive overview of various low-power design techniques as well as the corresponding, recommended verification steps. You will be provided with complete understanding of what it takes for low-power signoff. Topics covered include:​

• Generation, optimization and maintenance of UPF throughout the flow​
• Static low-power checks at different stages of the design and verification flow, from UPF creation to gate-level design connected to power-ground (PG) pins​
• Formal connectivity checking and property verification in the presence of low-power elements in the design, including optimization of clock gating and retention to improve PPA​
• Dynamic, low-power simulation to further ensure design functionality in the presence of UPF​
• Debug of issues that arise during low-power verification​

You will hear from low-power experts to gain a solid understanding of steps to implement and verify a solid low-power strategy that reduces silicon power consumption.  This practical knowledge will prepare you for the trend of ever lower power consuming designs. ​

Workshop - FPGA Prototyping for Large Multi-Die/ Multi-Core Designs

Presenters: Joe Marceno (Synopsys); Sivaramlingam Palaniappan (Synopsys)

Date & Time: Thursday, March 7 - 11:00am -12:30 pm / Room: Donner

Abstract: 

Today's design size and complexity continue to increase putting greater pressure on meeting compile time and performance goals of the prototype. Together, they are increasing faster than the available compute capability. This has led to more challenging implementation problems and longer, unpredictable bring-up times for prototypes. To decouple design sizes and compute capacity, a divide-and-conquer approach is needed. This approach helps to enable parallelism. ​

This workshop will present enhanced capabilities in Synopsys HAPS ProtoCompiler that can enable parallelism - allowing different teams to solve implementation challenges independently and concurrently. In addition, we will discuss how parallelism enables reuse of such implementations for design types involving multi-cores which are often replicated, ultimately reducing peak compute requirements and leading to faster tool execution times. This modular design approach is a framework that will address these needs while also providing a path to faster incremental TaT.