Why Attend?

Embedded world delivers unprecedented insight into the world of embedded systems, covering everything from components and modules to operating systems, hardware and software design, machine-to-machine communication, services, and the intricacies of complex system design. ​

Synopsys will be in Hall 4 highlighting our solutions to accelerate your automotive software development and integrate security IP into your designs. We will be in Hall 5 with solutions to speed time-to-market for your RISC-V SoCs.

We will also be presenting at the sessions listed below. 

We look forward to seeing you there!

Synopsys Booth Expo: Hall 4-222

Automotive Solutions: Virtual Prototypes for automotive software testing and automated system testing

Security Solutions: Industry’s broadest Security IP portfolio protecting against evolving threats

RISC-V International Pavilion: Hall 5-119

Software Development Solutions: Synopsys IP and verification tools to enable fast SoC development

Synopsys Solutions in Partner Booths

Synopsys PCIe 7.0 IP PHY IP in an interop demonstration with Teledyne LeCroy's equipment

Teledyne LeCroy | Hall 4-304

Synopsys Automotive VDK capabilities

Green Hills Software | Hall 4 - 325

HighTec EDV Systeme | Hall 4 - 432

Lauterbach | Hall 4 - 210

PLS | Hall 4 - 310

Tasking | Hall 4 – 255

VDKs at Semiconductor Partners

Infineon | Hall 4A - 138

NXP | Hall 4A - 222

Synopsys Presentations


RISC-V Pavillion, Hall 5-119
Tue. March 11, 2025
04:00 - 04:15 PM CET
More Than Point Tools: RISC-V Solutions
  • Larry Lapides, Exec. Dir., RISC-V Tools Business Development
Session 7.4: EDGE AI - Hardware for Edge AI
Wed. March 12, 2025
10:30 - 11:00 AM CET
Multi-die Design for Edge AI Applications
  • Hezi Saar, Executive Director for Mobile, Automotive, and Consumer IP
RISC-V Pavillion, Hall 5-119
Wed. March 12, 2025
12:00 - 12:15 PM CET
Embedded Applications Get a Helping Hand: Extensible ARC-V Processors
  • Rich Collins, Sr Director, Product Management, ARC-V Processors & Ecosystem
Session 4.6: HARDWARE DESIGN - Memory: Test for Zero Defect
Wed. March 12, 2025
02:30 - 03:00 PM CET
An Easy RTL Approach to Boost up IP Subsystem Scan Test Coverage
  • Shanshan Zhou, Sr Manager, EDA Group

We'll See You There!