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ASIP University Day 2018 Europe Proceedings
Synopsys and the RWTH Aachen University / Germany held the ASIP University Day 2018, an informal workshop to learn more about the exciting options ASIPs offer, and what it takes to develop them. ,
Application-specific instruction-set processors (ASIPs) are an ideal solution when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. As a result, ASIPs have become a third implementation option for modern SoCs, co-existing with standard processors and fixed hardware, with heterogeneous multicore systems now becoming the standard.
Applications such as 5G new radio, data centers, artificial intelligence, or automated driving assistance have fueled the development of such ASIPs, and have triggered many university projects. Processor design projects such as the RISC-V initiative at UC Berkeley also initiated a lot of interest in designing specialized, application-optimized processor architectures.
On September 26th, Synopsys, in cooperation with RWTH Aachen University / Germany, organized the ASIP University Day 2018. Leading university teams presented results from their ongoing ASIP projects in domains such as 5G baseband and AI accelerators. Synopsys presented latest case studies and in-depth insight into the ASIP Designer™ technology. Teaching embedded processor design classes, and how to leverage ASIP Designer, was another subject of the day. To close the event, a reception allowed plenty of time for networking among participants. See here the Agenda topics of the day, and contact us if you would like further information.
Agenda
| Abstract |
| ASIPs in System-on-Chip Design: Market and Technology Trends Markus Willems, Synopsys ASIPs have established themselves as an implementation option next to standard processors IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability. This talk will provide an introduction into Synopsys' ASIP Designer tool-suite, targeted markets, business models, and how Synopsys collaborates with university partners in this domain. |
| ASIP Designer at ETH class: Extending the RISC-V ISA for Efficient Near-Sensor Data Analytic Algorithms Pasquale Davide Schiavone, ETH Zuerich Minimizing the power consumption is highly desirable to achieve multi-year lifetimes for battery-powered IoT endnodes . These endnodes are usually based on programmable microcontroller-class platforms to reduce the time-to-market and increase the products versatility. The PULP open-source project is a joint effort between ETH-Zurich and UniBologna which aims to develop an energy-efficient programmable platform based on the RISC-V ISA. Custom extensions to the ISA are possible for RISC-V cores thanks to the openness of the ISA and the availability of unoccupied regions in the opcode space. These extensions are key to increase the energy-efficiency in IoT applications when near-sensor data analysis is needed. To help students of our classes to understand how to extend a RISC-V core, we used ASIP Designer to explore processor customization using a fast and highly automated design flow. |
| Designing Application-Specific Processors for Deep Learning Acceleration Gert Goossens, Synopsys Deep learning is making its way into various application domains. The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNN). Algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate by example how ASIPs reconcile the needs for performance and flexibility. |
| Design Perspectives of an ASIP for CNN Acceleration Andreas Bytyn, RWTH Aachen The rise of Convolutional Neural Networks (CNNs) has created the need for highly parallel processing architectures. While using systolic arrays yields the desired parallelism, most of the flexibility is lost. We present the design perspectives and challenges encountered while implementing a 4-slot VLIW processor with SIMD instructions that attempts to bridge the gap between performance and flexibility. |
| Wireless Case Study: Minimum Mean Square Error (MMSE) Equalization in 5G New Radio Werner Geurts, Synopsys ASIPs see strong adoption in the field of 5G wireless communication. ASIPs enable product development before the 5G standard is finally frozen. At the same time, ASIPs provide the acceleration needed to achieve the high throughput and short latency requirements of 5G. As an example we will show the design of an ASIP for MMSE in 5G New Radio. We follow an “algorithm first” design process. Such process starts from a number of algorithms for which the architecture has to be optimized, and the definition of the throughput requirements. The presentation will provide an overview on main functional kernels of the MMSE algorithm, and the performance requirement in the context of the 5G standard. We will illustrate the architectural decisions that have to be taken, and how this process is being supported by ASIP Designer. |
| ASIP Design for massive MIMO Baseband Processing Steffen Malkowsky, Lund University We present the current status of our 16-lane complex SIMD massive MIMO ASIP with planned features like pre- and post-processing slots for efficient mapping of massive MIMO signal processing algorithms as well as a specialized architecture to boost matrix calculations. |
| Custom Processor Design for Bayesian Networks Nimish Shah, KU Leuven A Bayesian network is a graphical model that represents probabilistic dependencies among a set of variables via a directed acyclic graph (DAG). Its ability to model causal relations and uncertainty, handle missing data, and perform interpretable inference, makes it a powerful tool for machine learning. Often large Bayesian networks with hundreds of nodes are required to model real-life problems, and inference is made tractable by compiling these networks into circuits of sums and products, called arithmetic circuits. Yet, state-of-the-art is missing processors capable of efficiently computing such arithmetic circuits for energy-efficient embedded inference in Bayesian networks. We are developing a processor with a custom datapath that can exploit the typical data flow patterns in arithmetic circuits, using Synopsys ASIP tool. A preprocessing algorithm is developed to decompose an arithmetic circuit into processor-suitable subblocks, to assist the ASIP tool in the compilation. |
| Technology InDepth: C/C++ Compilation Using ASIP Designer Gert Goossens, Synopsys ASIP Designer provides a C/C++ compiler even for highly specialized processor architectures. We will explain in detail the underlying concepts of this patented technology, and how to take advantage of it in your ASIP project for both architectural exploration and embedded software development. |
ASIP Designer Tutorial/Training
The ASIP University Day 2018 was complemented by a free training/tutorial day on September 27th, with students diving deeper into the concepts of the nML language.