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ASIP Newsletters
Read this issue to learn about the ASIP Designer™ V-2023.12 release, which introduces a new product “ASIP Designer Advanced Verification Add-On” that offers new and updated features including formal ISA verification support, automatic test program generation for hazard rules and an extra license for random instruction sequence generator.
In this issue, learn about Tsec, new example processor model, which implements an accelerator for post-quantum cryptography. Also find out about the latest enhancements in the U-2023.06 release of ASIP Designer, including updates to the processor models library, processor modeling, and C/C++ Compiler and various other extensions.
In this issue, learn about the enhancements made to the ChessDE graphical IDE in the T-2022.06 and U-2022.12 ASIP Designer™ releases to improve the user experience and increase productivity. These enhancements include easier context-aware navigation in the editor, various new visualization capabilities in profiling, and more user-friendly feedback of the compiler’s scheduler.
ASIP eUpdate, February 2022
Read this issue to find out about the broad RISC-V ISA based model library that is available as a starting point for your next proprietary ASIP accelerator design. Also learn about the new ASIP Designer™ release schedule and see what’s new in the S-2021.12 release of ASIP Designer.
ASIP eUpdate, April 2021
Read this issue to learn how ASIP Designer leverages access to Synopsys design and verification methodologies, tools, and expertise to enable PPA-optimized processor design with an instruction-set tailored for a domain or set of applications. This newsletter also describes what's new in the 2021.03 release of ASIP designer and covers upcoming ASIP events.
ASIP eUpdate, October 2020
Read this issue to find out how ASIP Designer’s Simple Datapath eXtensions (SDX) simplify the implementation of a customized RISC-V ISA. This newsletter also describes what’s new in the 2020.09 release of ASIP Designer and covers upcoming ASIP events.
ASIP eUpdate, April 2020
Read this issue to learn about the LLVM frontend extension that offers full C/C++ language support and powerful high-level optimizations while supporting ASIP architectures. This newsletter also describes what’s new in the 2020.03 release of ASIP Designer and covers upcoming ASIP events.
ASIP eUpdate, November 2019
This issue describes instruction level parallelism (ILP), a proven architectural feature through which the performance of processor architectures can be increased. This newsletter also describes what’s new in 2019.09 release of ASIP Designer and covers upcoming ASIP events in November and December 2019.
ASIP eUpdate, April 2019
In this issue of the newsletter, we will focus on architecture exploration, a key challenge for SoC designers to introduce differentiating advantages within the target product’s market window. This newsletter also describes what’s new in 2019.03 release of ASIP Designer and covers the latest ASIP customer successes, white papers and webinars.
ASIP eUpdate, October 2018
In this issue of the newsletter, we will focus on a range of debug methodologies that enable analysis of both hardware and software at all stages of the development process. This newsletter also describes what’s new in 2018.09 release of ASIP Designer and covers the latest ASIP webinars, datasheets, white papers and recent events..
ASIP eUpdate, April 2018
This issue of the newsletter features three models, Tgauss, Tcom8 and SHA256, and concludes the series on example models. It covers the technical features of the cores as well as the process of architectural exploration, illustrating the steps taken to arrive at the final architecture. These models are provided in source code, serving as a modeling reference and as a starting point for your own designs.
ASIP eUpdate, October 2017
In this issue of the newsletter, we will look at example processor models that demonstrate how to do a fast context switch. We will also describe several new and enhanced features in the 2017.03 and 2017.09 releases of ASIP Designer, including a further enhanced LLVM frontend, support for 64-bit address space, little endian support, enhanced debugging, further acceleration of instruction accurate simulators, and much more.
ASIP eUpdate, January 2017
Based on your feedback, example models that are provided with ASIP Designer is a topic of high interest so we decided to give even more room to it in this issue. The other main topics are an update on the 2016.09 release of ASIP Designer and the latest ASIP webinars, datasheets, white papers and upcoming events.
ASIP eUpdate, June 2016.
This issue covers the latest enhancements to ASIP Designer, the leading ASIP tool solution, and it highlights the wide range of processor models available to jump-start your design. This newsletter describes what’s new in 2016.03 release of ASIP Designer and also covers the latest ASIP webinars, datasheets, white papers and upcoming events.
ASIP eUpdate, December 2015
This issue describes the latest release of ASIP Designer (2015.12) along with several enhancements. It also covers the latest ASIP webinars, white papers, customer successes and more.
ASIP eUpdate, April 2015
This issue introduces ASIP Designer and covers the latest ASIP webinars, white papers, customer successes, application notes, and more.
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