Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial
Unrivaled Performance Efficiency for Embedded Applications
The Synopsys ARC® EM Family, based on the ARCv2 instruction set architecture (ISA) includes ARC EM4 and EM6, DSP-enhanced EMxD processors, and ASIL compliant EM functional safety processors.
The ultra-compact EM cores feature excellent code density, small size and very low power consumption, making them ideal for power-critical and area-sensitive embedded and deeply embedded applications.
The ARC EM processors are supported by a broad ecosystem of commercial and open-source tools, operating systems and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website.
Products
ARC Software Development Solutions
ARC Software Development Platforms:
- ARC EM Software Development Platform (feature rich FPGA based platform)
- ARC IoT Development Kit (silicon based platform)
ARC Development Tools and Software:
- MetaWare Development Toolkit (compilers, debugger, and simulator)
- MQX RTOS
- embARC Open Software Platform (comprehensive suite of free and open source software)
- ARC Access Program (portfolio of 3rd party tools, operating systems, and middleware)
Products and Licensable Options
Features
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
- Harvard architecture for higher performance through simultaneous instruction and data memory access
- High-speed pipeline designed for maximum power efficiency
- 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
- Add or omit hardware features to optimize the core for your target application - no wasted gates
- The ARChitect wizard enables drag-and-drop configuration of the core
ARC Processors EXtension (APEX) technology enables users to customize their processor implementation.
- Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
- Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance