Student Design Contest

Contest Scope:

• Teams will create a complete schematic and DRC/LVS clean layout of a design according to contest specifications using the Synopsys Custom Compiler flow.
• Teams will be required to use the Synopsys 32/28nm Interoperable Process Design Kit.
• All designs submitted must be original work – designed and drawn by the student teams for this contest. Designs may not have been previously used or directly copied from other sources. This will result in immediate disqualification.

Prizes:

• First place – 30,000 INR
• Second place – 10,000 INR

Contest Rules:

•  Maximum of one team per university/college/institution in India may be nominated.
• Two students per team (final year Bachelor engineering students or Masters engineering students only)
• One advisor (professor or department head) will nominate the team and act as sponsor and the first line of support for the team during the contest.
• Cash prizes will be awarded equally between the student team members. (The advisors will not participate in cash prizes.)

Eligibility:

• The affiliated university/college/educational institute is not required to be an existing Synopsys University Program customer in India with the necessary EDA tool access (see Required Skills & Tool Knowledge).
  
• An individual may only be a member of one team and may only submit one contest entry.
• Employees and contractors of Synopsys or its affiliated companies, and their parents, spouses, children, siblings, and members of their households, are not eligible to participate in the contest.
• All team members must be eligible under the contest rules in order for any team member to receive a prize.

Required Skills & Tool Knowledge:

•  Teams must be able to demonstrate working knowledge of the following technical skills:

- Analog integrated circuit features, design and analysis methods of basic analog circuits

- Principles of analog circuit techniques, variants, improvement methods of parameters, research of structures, analysis of different basic analog IC parameters

- Differential and operational amplifiers, switched capacitor circuits, oscillators, phase looked loops, data converters, secondary power sources, etc.

•  Teams must have familiarity and experience using the following or equivalent tools/systems:

- Custom WaveView™, Custom Compiler™, HSPICE®, IC Validator, StarRC™

- Linux/Unix OS, including the usual commands needed for running EDA tools

How to Nominate a Team:

Teams can only be nominated by a university/college/institute professor or department head that will sponsor and support the team during the contest.

• The contest is limited to 40 teams. Once all nominations are submitted and reviewed, teams will be notified of their status by July 2017.
• Both team members must be available to attend one 3-day training workshop in either Hyderabad, Noida, or Bangalore . No funding will be provided by Synopsys for travel or stay during training*

Evaluation Criteria:

Project submissions will be evaluated by the contest committee members and judged based on the following criteria:

• Functionality demonstrated through HSPICE simulations
• Optimal area of layout that is DRC/LVS clean
• Effective use of design productivity features available with the tool flow
• Results that demonstrate close matching of given design specifications through pre-layout and post-layout HSPICE simulations

The decision to accept any contest entry and all judging decisions will be made by the contest committee in its sole discretion and will be final. In the event Synopsys determines that one or more prize winners are ineligible according to the contest rules, Synopsys reserves the option to award no prize, or to award a prize to an alternate contest participant.

Timeline: