Call for Content

AI AND MACHINE LEARNING

• Improving productivity and achieving faster quality of results with AI and machine learning 
• Using implementation tools to enable the highest-performance AI designs
• Formal verification of data path designs 
• Using emulation for AI software stack validation
  
• Productivity and performance innovations using AI-driven EDA tools
• Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications 
• The challenges of designing and integrating AI accelerators
• Using AI to enable rapid analog and digital node migration

AUTOMOTIVE

• Accelerating automotive software development and validation with virtual prototyping
• End-to-end functional safety verification with fault simulation, formal and static verification
• High-reliability design techniques for automotive designs
• Implementing safety critical designs for automotive applications
  
• Designing ISO 26262 required in-system test using Synopsys tools
• Accelerating ISO 26262 certification with ASIL-ready certified IP

ANALOG/MIXED-SIGNAL DESIGN AND SIMULATION    

• Addressing analog, custom digital or memory design verification turnaround time bottlenecks with heterogenous compute acceleration
• RF analysis of RFIC or analog periodic circuits
• Ensuring AMS design robustness with advanced variability analysis
• Minimizing design margins with integrated power/signal net electromigration/IR drop analysis
• Improving AMS design robustness with analog circuit electrical rule checking
• Best practices in mixed-signal verification with a digital verification methodology 
• Verifying power and signal integrity for multi-gigabit circuits
• Accelerating pre-layout design centering & optimization
• Custom layout productivity gains using Synopsys tools
• Mixed custom/digital implementation productivity gains using Synopsys tools 
  
• Accelerating analog design closure 

BIG DATA ANALYTICS

• Accelerating root cause analysis with AI-driven data analytics
• Using analytics to optimize power, performance, and area targets
• Using analytics to understand the ecosystem health and silicon life cycle management

DESIGN AND VERIFICATION IN THE CLOUD

• Performance vs. cost trade-offs for design or verification in a cloud environment
• Security concerns and best practices in migrating from on-premises to cloud for design and verification
• Allocation and usage of cloud resources for library characterization, simulation, timing analysis and parasitic extraction
• Maximizing available resources with physical verification elastic CPU usage
• Impacts on design size partition for physical implementation in a cloud environment
• Exploring the impact on design size partition using physical implementation in a cloud environment 
• Leveraging tool runtime scalability in the cloud; what worked best 

DIGITAL DESIGN IMPLEMENTATION

• Optimal design flow for digital implementation at advanced node designs 
• Advanced place & route to meet PPA targets 
• Accelerating time to results for large designs 
• Shift left convergence by improving constraints and RTL restructuring 
  
• How to achieve optimized performance, power and area for Arm CPUs
• Using parallel processing to accelerate physical and full-chip timing signoff
• Accelerating full-chip turnaround time for large designs using physical signoff 
  
• Early time-based peak power analysis using RTL-based vectors 
• Using physically aware ECO capabilities to improve PPA and accelerate timing closure 

ELECTRICAL LAYOUT VERIFICATION

• Full-chip ESD verification
• Transient ESD effects
• Power device reliability
• Improving power device efficiency

ENERGY-EFFICIENT SoCs

• Low-power design for smart edge devices
• AI-driven power considerations
• The quest for energy efficiency: evaluating hardware and software approaches
• Transistor-level vs. system-level energy optimization
• The special power demands of crypto chips

MULTI-DIE SYSTEM

• Enabling next-generation HPC designs with multi-die design and methodology 
• Multi-die architectural planning and chip-package co-design  
• Golden parasitic extraction and signoff analysis for multi-die designs
• Extending the envelope of Moore’s law with multi-die design 
  
• Higher productivity with co-design & multi-die design for 2.5D/3D memory devices

MEMORY

Design Technology Co-optimization:

• Memory technology exploration (novel devices, process recipes) with TCAD and SPICE
• Memory technology pathfinding with virtual PDKs
• Faster design closure with In-design lithography rule checking 

Design Shift Left:

• Faster block/chip-level simulation TAT
• Faster PDN simulation with heterogenous compute (CPU + GPU) acceleration
• ML-driven high sigma Monte Carlo analysis for library characterization
• Faster physical verification on memory designs with ML-driven scheduling and distributed processing
• Faster design closure with pre-layout parasitic estimation

Digitization:

• Mixed-signal verification flows for memory data path
• Static timing analysis for embedded memories
• Timing robustness with MOS aging-aware static timing analysis
• Automated place & route for memory periphery

Silicon Reliability:

• Higher coverage with circuit electrical rule checking
• Fast chip-level EM/IR analysis w/ PDN
• Functional safety analysis and ISO 26262 compliance for memory IP with analog defect simulation
• Analog test coverage improvement with analog defect simulation
• Faster silicon failure analysis with analog defect simulation
• Silicon lifecycle management for memory IP
• Memory protocol verification and coverage closure

PHYSICAL VERIFICATION

• Leveraging multi-CPU scalability for fast time-to-results 
• Dirty design handling during SoC integration to minimize runtime and maximize productivity 
  
• Shift-left physical verification analysis and repair  
  

SECURITY & SAFETY

• Strategies to reduce chip vulnerabilities through hardware, IP or software approaches 
• The role of an SoC-based root of trust (RoT) for security 
  
• How to leverage standards to enhance safety and security 
  
• Hardware and software approaches to implementing functional safety 
  
• Hardware security verification 
  

SIGNOFF

• How 3DIC design changes signoff
• AI algorithms and their impact on signoff
• Balancing timing, power, power/signal integrity closure

SILICON TEST AND LIFECYCLE MANAGEMENT

• Success with early RTL analysis, physically aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
• Use of software analytics for accelerating product introduction as well as improving yield, test times and quality during high-volume production
• Highlighted SoC application areas include AI, automotive, mobile and processors
• Integration of PVT sensor IP monitors and subsystems for enhanced device screening, power and performance optimization, and enhanced field performance/security 

SUCCESSFUL IP INTEGRATION INTO SoCs

• Interface IP such as 112G Ethernet, Die-to-Die, PCIe 5.0, DDR5/LPDDR5, etc.
• Embedded ARC processors & embedded vision processors
• OTP NVM, embedded memories & logic libraries in advanced FinFET processes
• Integration of IP into high-performance computing, automotive, AI/ML or IoT designs

VERIFICATION HARDWARE

• Accelerating software bring-up with emulation and prototyping
• Software-driven power analysis for GPUs and AI
• Prototyping with real-world interfaces
• Large complexity prototyping
• Pre-silicon networking system validation
• SoC performance validation using emulation
• Trust and hardware security verification
• DFT-driven emulation
• Prototyping approaches for 2.5D/3D heterogeneous integration
  
• The use of digital twins
  

VERIFICATION SOFTWARE

• Faster and better convergence using formal methods
• Verification coverage planning and closure
• Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
• Accelerating verification and debug for advanced protocols
• Innovations in verification methodology for optimized performance