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In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.
Overview
AMBA ACE5-Lite interfaces are used by I/O coherent managers that need to communicate to other fully coherent managers with caches in the system. Typically, AMBA ACE5-Lite interfaces are used alongside Arm AMBA 5 CHI RN-F interfaces as shown below.
Arm AMBA ACE5-Lite Interfaces on a Cache-Coherent Interconnect
The Arm AMBA ACE-Lite protocol specification is a subset of the Arm AMBA ACE5 specification. The AMBA ACE-Lite interface is one-way coherent or “IO-Coherent” which means it can snoop the fully coherent processors with caches. AMBA ACE-Lite is used by manager components that do not have hardware coherent caches, but are required to:
- Indicate if issued transactions could be held in the hardware coherent caches of other managers
- Issue broadcast cache maintenance operations
An example of an AMBA ACE-Lite manager is a graphics processing unit (GPU).
New Features of AMBA ACE5-Lite:
The new AMBA ACE5-Lite protocol caters to enhanced performance and efficiency of key Arm architecture features, as well as aligns with the Arm AMBA5 CHI (coherent Hub interface) protocol. Some of the key features of the AMBA ACE5-Lite protocol include:
- Atomic transactions: Various atomic operations to be performed closer to where the data is located thus making it efficient and streamlined
- Cache stashing: Install a cache line in the cache of another component in the system, moving it closer to the point of use and improving the overall system performance
- Cache de-allocation transactions: ReadOnceCleanInvalid and ReadOnceMakeInvalid de-allocating transactions, combine ReadOnce transaction with cache line invalidating CleanInvalid or MakeInvalid transactions
- These are used to read the cache line data and de-allocate it in the remote cache when that cache is no longer required helping to ensure better availability of the cache resources in the system
- Some other key features include: data protection and poisoning signaling, new DVM messages to support Arm architecture requirements, QoS accept signaling, and persistent cache maintenance operations
Synopsys supports Arm AMBA ACE5-Lite
Synopsys VIP for Arm AMBA ACE5- LITE supports the Verification IP components for Arm AMB ACE5-Lite with the functionality, checks, functional coverage, and verification features. The Synopsys VIP for Arm AMBA CHI solution provides system monitoring across AMBA ACE5-Lite and AMBA CHI components around the Coherent Mesh Networks. In general, Synopsys VIP addresses all the challenges of verifying AMBA ACE5-Lite interface-based designs and ensures cache coherency across multiple cluster SoCs.
All Synopsys VIPs for Arm AMBA protocols are written in native SystemVerilog and offer simulation run time and compile time performance advantages. The Synopsys VIP for Arm AMBA ACE5-Lite offers protocol-aware debug, source code visibility and error diagnostics that eases time to debug process. Synopsys VIP also enables users with efficient verification measurement by offering built-in coverage, graphical integration with the prebuilt verification plan, and sequence collections.
Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.
You can read some of our past AMBA-related blogs here. To learn more about Synopsys VIP and Test Suits for AMBA protocols please visit http://synopsys.com/vip
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Sep 12, 2024
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