Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip

Manuel Mota

Dec 14, 2023 / 4 min read

Stephen Wong, principal engineer at Intel, co-authored this blog post. 

Late this summer, Synopsys and Intel marked a milestone achievement at the Intel Innovation 2023 conference, with the world’s first Universal Chiplet Interconnect Express (UCIe) interoperability test chip demonstration showing robust UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP.

The successful UCIe test chip demonstration is the latest achievement over the course of a long-standing collaboration between Synopsys and Intel. Seeking to demonstrate working interoperability, Intel got the process started by reaching out to Synopsys, one of the first in the industry with available UCIe IP. The effort involved multiple teams spread across the world. In addition to package design, the teams engaged in a substantial amount of work pre-silicon to uncover issues by simulating each test chip using Synopsys VCS® functional verification solution.

Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology. It was paired with a Synopsys UCIe IP test chip, fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable. 

first ucie chiplet intel synopsys

Lessons Learned to Move Multi-Die Systems Forward

Multi-die systems are becoming an answer for many application areas as bandwidth demands soar to new heights. Through heterogeneous integration of multiple dies in a single package, a multi-die system delivers greater levels of processing power and performance for AI, high-performance computing, and hyperscale data centers. An array of technological innovations has paved the way for the emergence of multi-die systems, a critical one being the UCIe standard. Introduced in March 2022, UCIe is considered the de facto standard for die-to-die connectivity, helping to enable a broader ecosystem of vetted dies, or chiplets.

Through their collaboration, the Synopsys and Intel teams uncovered some lessons learned that they plan to share with the UCIe Consortium, which oversees the standard and is developing a compliance program for the standard. Among some of the lessons:

  • As silicon design and manufacturing become more complex, and validating that everything works as intended is also cost- and time-intensive, finding a way to use existing test chips or silicon can be an ideal way to assess compatibility.
  • Designing multi-die systems involves extensive planning, especially if you plan to re-use package or board designs. Building in as much flexibility as possible in the boards is one way to provide options for future use.
  • An open standard like UCIe provides confidence of interoperability. When one company controls both sides of a link, there are, of course, no concerns about whether each side will work together. But moving forward, we’ll likely start seeing more companies who prefer not to build both sides, instead choosing to buy components off the market.
  • By allowing partitioning of a design to include multiple process nodes, chiplets help to mitigate the expense of manufacturing at advanced nodes. Without a standard, IP availability is limited, and choosing a process node based on IP availability isn’t an optimal approach. The UCIe test chip interoperability demo provides a solid proof point for mixing and matching IP designs and lays the foundation for an open chiplet ecosystem. 

Interoperability Demo Opens Pathways for Custom Silicon

One of the advantages of a multi-die system architecture is that it can consist of dies from different vendors for different process nodes. This provides flexibility in terms of cost and in optimizing power, performance, and area (PPA). UCIe is a key ingredient to bring the disparate components together, enabling them to communicate with one another while supporting a range of advanced packaging technologies. The UCIe Consortium sees UCIe as an enabler of an open chiplet ecosystem. Such an ecosystem could potentially spark new waves of custom silicon innovation to meet relentless performance demands of an era where AI, connectivity, and cloud computing are becoming ubiquitous.

While a UCIe-compliant multi-die system may work well through development, testing, and manufacturing, you’ll also need to ensure that the system’s die-to-die connectivity will remain reliable from the start and in the field. This is where UCIe IP plays an integral role. UCIe IP typically consists of a controller for low latency between dies based on common protocols, such as PCIe, CXS, and Streaming protocols; a PHY for high-performance and low-power connectivity in a package; and verification IP to accelerate verification closure. Built-in testability features enable you to root out defective dies at the naked die testing phase. In addition to these testability features for known good dies, the IP can also provide cyclic redundancy checks (CRC) or parity checks for error detection and retry functionality for correction of detected errors.


Synopsys and Intel plan to continue collaborating to further expand the UCIe ecosystem. Meanwhile, adoption of multi-die systems is increasingly widespread and expected to be mainstream in the coming year. Close collaboration across the semiconductor ecosystem will be essential in enabling chip designers to realize the benefits of these complex, interdependent designs. As they become the architecture of choice for many more sectors, multi-die systems can potentially open new avenues of innovation to meet the demands of our hyperconnected digital world. 

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