Improving Semiconductor Yield with Test Data Analytics

Guy Cortez, Randy Fish

Jun 27, 2022 / 11 min read

In the semiconductor manufacturing world, there’s a constant drive to reduce cost. Any increase in the number of working chips on a wafer, after all, directly impacts the bottom line. However, as chip designers work to pack more transistors onto their chips and take advantage of new packaging technologies, the chips become more challenging to manufacture—and a high yield becomes more difficult to attain.

What if you could tap into the volumes of data collected by semiconductor testers and find insights to help you address potential problems early on, before these issues lead to repeated (and time-consuming), costly tests or, worse, failed die? Real-time, automated data analytics provides a way to do this.

In this blog post, we discuss our recently announced collaboration with Advantest, a leader in semiconductor test equipment. This collaboration addresses real-time data streaming from test floors distributed across the semiconductor supply chain to analytics platforms hosted by chipmakers. The resulting solution provides chipmakers with the insight they need to find and fix problems earlier in the process to maximize yield while also minimizing test costs and eliminating quality escapes.

Silicon wafer in die attach machine

What Makes Semiconductor Data Management So Challenging?

Outsourced semiconductor assembly and test (OSAT) facilities provide packaging and test services to chip design teams. Their work happens at the back end of the flow, just before chips are integrated into end devices. From semiconductor fabless companies that don’t have the infrastructure for packaging and testing their devices to semiconductor foundries that focus primarily on the front end of the line, the demand for OSAT facilities is robust. In our smart everything world, where semiconductors are in such high demand, OSATs play a critical role in the electronics industry supply chain. They are essential in enabling access to the valuable data they host in their test environments.

Traditionally, collecting and analyzing test data from silicon devices being tested on automated test equipment (ATE) is nothing new. However, historically, it’s been a manual process that hasn’t happened in real time. As such, the insights gleaned often come too late to make a difference to the end product. Typically, a technician on the test floor at the OSAT produces Standard Test Data Format (STDF) files from each tester only after each wafer is tested or after a lot or sublot worth of packaged devices has been tested before the data is uploaded into a cloud-based server environment. From there, the data can be accessed by analytics software. By the time the analysis is completed, however, it may be too late to address any issue before the affected dies are further along downstream in manufacturing. Even in cases where the dies in question can be intercepted, many more dies may have been impacted by that same issue. The amount of retest and related test costs required after determining the proper corrective action is significantly higher than if the issue was addressed in real time. There are also opportunities when using manual efforts for someone to intercept the test files containing the data, raising security questions.

Another important consideration is how vast and diverse the manufacturing and testing ecosystem can be. Manufacturing and test operations are often spread across the world, supporting the various stages of chip manufacturing. Independent suppliers continuously generate high volumes of various types of chip data in different formats. Managing this data is quite challenging on many levels, from collecting and storing it, to monitoring and aligning it for quality and, ultimately, analyzing it for useful insights. Therefore, moving to a real-time automated data collection process has many benefits.

Turning Chip Data into Actionable Insights

Automating the process via an application programming interface (API) that brings the data straight—and continuously—from the testers to the analytics tools more effectively transforms the data into immediate actionable insights. This is the idea behind the real-time data analytics solution developed by Advantest and Synopsys. The solution is based on the new Advantest Cloud Solutions™ (ACS) Nexus real-time data streaming infrastructure and the Synopsys SiliconDash data analytics solution for high-volume semiconductor manufacturing and test. ACS Nexus is a real-time data streaming infrastructure that, via a central and standardized software interface, provides access to aggregated data streams from multiple test cells. The infrastructure is tightly integrated into Advantest equipment platforms. The SiliconDash solution, part of the Synopsys Silicon Lifecycle Management Family, provides comprehensive, real-time intelligence and control of manufacturing and test operations of IC and multi-chip module (MCM) products for OSATs, fabless companies, foundries, and integrated device manufacturers (IDMs).

Advantest enables an analytics ecosystem for its semiconductor manufacturing equipment platforms. In this ecosystem, Advantest’s teams, customers, and third parties can develop advanced machine learning and data analytics solutions. Working together, Advantest and Synopsys have created a way for data, via an API, to be automatically loaded to the cloud for real-time access by the SiliconDash solution. From there, the solution provides real-time systematic and fully automated data preparation and analytics based on data streams from the whole manufacturing chain, including geographically dispersed manufacturing and test operations. Users get instant, out-of-the-box access to detailed dashboards, visualizations, reports, and valuable insights highlighting issues or key points of interest automatically and without any special querying or manual manipulation of datasets by the user. They also benefit from the assurance that the test data is collected securely and reliably.

Semiconductor Data Analytics Use Cases

With this data at their fingertips, users can take advantage of a variety of use cases:

  • Prompt root-cause identification via automated part-level traceability and analytics across the entire supply chain. Note that an electronic chip ID (ECID) embedded within the die or a 2D barcode that is etched onto the substrate or marked onto the resin is required to do end-to-end traceability across the various manufacturing stages.

For example, what if a volume of parts get through most of manufacturing where a majority pass their requisite tests during wafer sort (WS), go through assembly (ASSY), and are put into expensive MCM packages, only to find out that you are now encountering yield issues unexpectedly during final test (FT)? Experiencing late-stage systematic failures can be catastrophic if not resolved quickly. You run the risk of not being able to deliver your product to your end customers on time and may incur severe costs if you have to discard these expensive packaged parts and/or go back to an earlier stage in manufacturing to fix the problem. So, time is of the essence and real-time identification of critical late-stage issues can help lessen the impact.

Semiconductor Manufacturing Process Diagram | Synopsys

Root-cause analysis can be achieved by automatically correlating the failed bin results from the packaged parts during FT against all available manufacturing test data prior to this FT stage. The goal is to look for a parameter upstream that can predict this downstream issue seen during FT and correct the problem there.

  • Real-time, automated production control through the use of preconfigured libraries of recipes, algorithms, and scripting support facilitates test quality controls.

For example, a device under test (DUT) stuck in a socket can cause the untested chip to ship as a good unit. In a normal run, parametric data should be different for each tested part. Through observations of data reported in real time, a technician can be flagged when the data does not change, indicating that there is a problem, and then abort the test and remove the stuck part.

Semiconductor Production Control Diagram | Synopsys

Another example pertains to bad chip trimming. This is the case where misaligned test equipment requiring recalibration can manifest in a parametric shift of results during chip testing. If not corrected in a timely manner, this situation may lead to good parts failing and potentially being discarded (in other words, unnecessary yield loss). At a minimum, you will be required to retest many parts, potentially upwards of a full lot.

Here is an example of one of the sites on a tester load board that is testing differently from the other test sites. With analytics, you can check for parametric shifts between sites and when the difference is greater than a certain percentage, you can notify the test engineer or operator or, if granted permission, can halt the equipment until this issue gets resolved. Note that you do not have to wait for the difference in parametric results between sites to be great enough that the parts fail. The goal is to catch this type of issue before the parts fail, running the risk of losing significant yield.

Semiconductor Cumulative Percentage Test Results | Synopsys

Using edge computing technology, however, you can detect gaps between sites immediately as they occur, which will prevent loss of potential good chips and limit any unnecessary retest.

  • Enhanced WS efficiencies. WS is a time-consuming, expensive step in the production process, commonly requiring several hours to test just one wafer in a lot. A bad probe site as noted in the previous use case, whether from corrosion, dirt, or a calibration issue, can cause dies tested on these faulty sites to fail one or more tests. Dies on the wafer that failed a test will get retested. Some may pass. But others, if retested by the same faulty sites, will end up failing again. Eventually, these failed dies will be binned out and discarded—potentially resulting in the loss of good parts. Data analytics can help to quickly identify these test equipment-related issues by observing consecutive fails on a particular probe site. However, the benefit of real-time analysis is that this issue can be resolved as it occurs within the testing of the same wafer before testing is completed. Otherwise, you’d have to wait for an STDF file to be created once the wafer has been fully tested to find you have this issue, forcing you to effectively retest the entire wafer again and endure additional test costs.
Semiconductor Die Testing Fails Example | Synopsys

  • Screening for outliers. In dynamic part average testing (DPAT), some parameters don’t have appropriate limits, while others have no limits at all, allowing “all” parts to pass and continue through manufacturing, including potential bad parts. Bad parts that go through production are considered quality escapes, which ultimately end up failing in your customer’s end product while in use. A good analytics tool would be able to inform you that your parametric tests do not have any limits and if you request a solution from the tool, it can automatically apply test limits based on the parametric distribution of results after a statistically significant number of units have been tested and results gathered.One common approach is to wait for 100 packaged dies during FT to be tested for a sufficient data sample size and then apply a Six Sigma distribution on the data to create the new test limits. If part identification is available (e.g. ECID), then you know which of these parts would fail if the new test limits were applied. In this case, you can reload those parts that were not tested with the new test limits again on the tester to uncover their identity. If they are the ones that would have failed with the new limits, you can simply bin them out and remove them as failed parts without having to actually perform any retest. However, if there is no part identification, then you will need to rerun all previously tested parts that passed on the tester before the new test limits were applied, since you have no way to identify which of these previously passed parts would actually fail under the new limits. Thus, you have to rerun each of the previously passed parts again on the tester for that given parametric test. The question becomes, how fast can I find this issue of having no test limit so I can not only prevent quality escapes but also limit how much retesting has to be done?The biggest benefit of real-time edge analytics is realized when there is no part identification and your parts are now packaged and going through FT. The traditional method of creating and analyzing an STDF file happens only when testing of one lot or sub-lot has been completed. With no part identification and finding out you have no limits on a parametric test, you will have to retest that entire lot or sub-lot once you have applied limits. Any part that fails the new limit will be screened at that point.Real-time analytics enables you to find this issue as it occurs at the beginning of testing one lot or sub-lot. This saves a tremendous amount of tester time by a factor of how many packaged parts there are in one lot or sub-lot. For example, the analytics tool will tell you immediately that you have a test without any limits, allowing you to continue to test your desired “sample” amount of parts before establishing your test limits, which would only limit you from having to retest that small sample amount. Optionally, you can have the test stop immediately and have the test engineer look to correct the test program by adding the intended spec limits.Advantest ACS Edge™ provides a high-performance, highly secure edge compute and analytics solution delivering fast algorithmic AI decision-making with millisecond latencies during test execution. ACS Edge can be used in outlier screening and for DPAT, for which real-time, in-situ decision-making during the packaged unit testing process has proven beneficial. For example, ACE Edge provides real-time analysis with minimal test time overhead while also not having to re-socket devices for retest even if there is no chip ID within the device.
Semiconductor Wafer Fabrication Test Limits | Synopsys


Applications such as AI, high-performance computing, and 5G are leading to more complex IC designs and packaging, making it more challenging to achieve high yield and quality while keeping test costs under control. Extending the advantages of silicon lifecycle management analytics in the silicon manufacturing supply chain, Advantest and Synopsys are providing chip manufacturers with real-time access to insights that can help them improve product yield, quality, and costs, ultimately delivering on enhanced engineering productivity and time-to-market for your products.

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