Addressing the Verification Challenges of Panel Self Refresh in eDP

VIP Expert

Jan 16, 2023 / 3 min read

Synopsys Verification IPs

What is eDP (Embedded Display Port)?

VESA provides a standardized set of DisplayPort interface features for use in an embedded display application. This embedded interface is referred to as “Embedded DisplayPort” (eDP) and is the electrical transport for video and auxiliary data between the system host (including graphics hardware) and display panel. eDP applications include notebook PCs, all-in-one PCs, tablets, smart phones, and other systems that incorporate the display panel with the video or graphics processor.

How eDP’s Panel Self Refresh Saves Power?

One of the eDP power reduction features is Panel Self Refresh (PSR) which provides partial update frame capability and enables power saving in the system when the image is static. When the system is displaying a static image in self-refresh mode, such as text, and then just a portion of the image changes, such as a cursor, PSR enables the GPU to only send that part of the image instead of the whole video frame. This feature helps to extend battery life in Notebooks and smart phones.

edp screen
notebooks and smart phones

How Panel Self Refresh Works?

The PSR feature enables system-level power savings when the displayed image remains static for multiple display frames. The Sink device stores a static image locally in the Remote Frame Buffer (RFB) within the Sink device and displays this image from the RFB, while the eDP Main-Link can be turned OFF. Other Source device functions can also be powered down for further power savings.

As shown in Figure 2, the Source device sends a total of 5 pictures/frames. The Source device will stop after frame 3 and restart after 2 frames time. The Sink device will display the video data from frame buffer.

It’s hard to verify this feature because the Source device must store the previous video data and the Sink device’s monitor need to know when the Source device’s PSR will be active.

psr functionality example

Figure 2: PSR functionality example

Verification Challenges of Panel Self Refresh in eDP

  • PSR is very hard to verify because the source device video data and Sink device data are asynchronous
  • Score boarding is another big challenge in the verification of PSR when Source is VIP and Sink is DUT. A typical test environment consists of a Transmitter (Source VIP) and a Receiver (Sink device DUT)
  • In Figure 3, we see an example of the Source device sending 3 frames with PSR being active at third frame, so there are 3 frames in scoreboard. Since PSR is active for 2 frames, the Sink device receives 3 frames but displays 5 frames and sends 5 frames to the scoreboard. In this instance, there will be a scoreboard mismatch as the number of frames between the Source and Sink will not match
psr scoreboarding example

Figure 3: PSR Scoreboarding example

Solution to Address Verification Challenges of Panel Self Refresh

Synopsys Display VIP provides debug features and hooks to track PSR situation for effective use in testbench for realizing the frame comparator as shown in Figure 4. Synopsys VIP provides the Source with video data by default and the data from the Sink DUT can be captured from the user’s interface. A comparison model can be constructed by using the debug features provided by the VIP and that is depicted in a diagram like this.

PSR2 Comparison model

Figure 4: PSR/PSR2 Comparison model


Synopsys continues to provide the industry’s first and most comprehensive protocol verification solutions. Synopsys VIP for eDP supports eDP 1.4 and eDP 1.5 and is a comprehensive solution for the verification of PSR. It also features display stream compression (DSC) for visually lossless low-latency algorithms, increased resolution and color depths, and reduced power consumption.

Synopsys VIP for eDP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Synopsys VIP can switch speed configurations dynamically at runtime and includes an extensive and customizable set of frame generation and error injection capabilities.

Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware systems, Synopsys ZeBu® and Synopsys HAPS® .

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