10K Resolution at 120Hz Display with DSC 1.2

VIP Expert

Apr 23, 2018 / 2 min read

With the arrival of HDMI 2.1 comes an array of remarkable features including the capability to support up to 10K resolutions at 120Hz. Such high resolutions are supported for a wider range of display applications such as externally connected displays (i.e. PC monitors and televisions), embedded display interfaces within mobile systems, and automotive infotainment systems. But with higher resolutions comes the requirement for higher bandwidth. In this blog, we will discuss, how VESA (Video Electronics Standards Association) DSC (Display Stream Compression) helps to achieve 10K resolution in HDMI.

The challenge: Higher bandwidth for higher resolutions

Higher bandwidth is required to support higher resolutions. For example, a 24-bit R: G: B 8K frame at 24Hz corresponding to VIC (Video Identification Code) 194 requires a bandwidth of 12 Gbps and a 24-bit YCBCR4:2:0 10K frame at 48Hz corresponding to VIC 213 requires a bandwidth of 12 Gbps. With deeper color modes, the bandwidth requirement increases.

The solution: DSC

HDMI 2.1 brings the ability to compress the video data using DSC 1.2 standard, thus reducing the bandwidth requirement. DSC, a standard developed by VESA, uses a low-latency algorithm to generate a visually lossless compressed image. Keep in mind, the term “visually lossless” does not equate to “mathematically lossless”. The DSC is a high-quality codec which is mathematically lossy, but the loss is not perceivable to the human eye.

DSC also reduces bpp (bits per pixel), and the table below shows the desirable effect of compression. For example, a 24-bit R: G: B image transports 24 bits per pixel. By applying DSC when the bpp is reduced to 12, the data rate required would be halved. If data can be compressed to 8 bpp, the result is even better, a 3:1 compression.

Comparison between data rates before and after DSC chart

The result after application of DSC is spectacular. When DSC is applied with a bpp of 12, the 24-bit R: G: B VIC 194 frame requires a bandwidth of only 6 Gbps over 3 lanes. Similarly, when DSC is applied with a bpp of 7.875, the 24-bit YCBCR4:2:0 VIC 213 frame can be transmitted at a data rate of 6 Gbps over 4 lanes.

How does DSC work?

The figure below explains the basic principle of DSC for an 8Kp60 frame (8K resolution progressive frame at 60Hz). At a single glance, the main observations are as follows:

  1. Hblank (The total number of blanking pixels in a video line) is replaced by HCblank (The total number of tri-bytes in the blanking region of a line of chunks).
  2. Hactive (The total number of active pixels in a video line) is replaced by HCactive (The total number of tri-bytes in the active region of a line of chunks).
  3. The entire frame is divided into slices.
  4. line of chunks replaces a video line.
Basic principle of DSC diagram

Effectively, the frame is compressed since HCactive is much smaller than Hactive and HCblank is much smaller than Hblank.

Looking ahead

Last year, Synopsys announced that Novatek adopted Synopsys’ industry first Verification IP and source code Test Suite for HDMI 2.1 and HDCP 2.2 to design their next-generation multimedia chips. VESA DSC 1.2 module is integrated in VC VIP for HDMI 2.1 as well as DisplayPort 1.4 to provide a complete solution for verification of the high end display designs supporting upto 10k resolution using compressed video. To understand DSC algorithm in detail, please refer our white paper – Analyzing the Losses in Visually Lossless Compression Algorithms.

Stay tuned for our next blog in this series to study the basic principle of DSC in detail, to find out how exactly the DSC model generates compressed active pixels.

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