Early Architecture Performance and Power Analysis of Multi-Die Systems

A multi-die system is a semiconductor device in which multiple homogeneous or heterogeneous dies are contained within a single package. Multi-die systems have been available for select uses for years, but they are gaining wider popularity and are expected to be used in a wide variety of end applications, including high-performance computing, automotive, and mobile. There are two main factors driving the increased deployment of this technology.

The first trend is the disaggregation of one large monolithic system-on-chip (SoC) into smaller dies (also referred to as chiplets). The second trend is aggregation, with the integration into one package a set of discrete chips previously sharing a printed circuit board (PCB).

Despite the clear advantages of multi-die systems, there are numerous new challenges that stand in the way of multi-die system realization. This white paper focuses on those challenges that can be addressed by early architecture exploration of multi-die systems, including:

  • System pathfinding
  • Memory utilization and coherency
  • Power/thermal management

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