In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets.


What Attendees Will Learn:

Synopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow, including pros and cons to the current approach and opportunities for new development. We’ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning, construction, extraction, and signoff. Finally, we’ll wrap up with conclusions and future work.


Listed below are the industry leaders scheduled to speak.

Kenneth Larsen

Product Management, Sr Director

Kenneth Larsen is a director of product management in the EDA Group at Synopsys, focusing on 3D Heterogeneous Integration and Advanced Packaging. He has 30 years of experience in IC design verification and validation. Before joining Synopsys, Kenneth was worldwide senior technical director at Mentor.  

Nitin Navale

Principal Member of Technical Staff

Nitin Navale has worked across AMD & Xilinx since 2008 and currently serves as Principal Member of Technical Staff in the CAD/Methodology team. His current role is Technical Lead for 3DIC Methodology, though he has previously also worked on design automation that ranges across STA, EM/IR, Thermal, ESD, SOC Floorplanning & Construction, IP Management, Netlisting, and Characterization. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois, Urbana-Champaign. Outside of work, he is consumed by his devotion to board games and strategy. He's also an avid musician who plays multiple instruments with an active interest in music theory.

Akshata Sonnad

Member of Technical Staff

Akshata Sonnad is a Member of Technical Staff at AMD, working on developing methodologies and flows for floor planning, signoff, and interposer/ InFO routing for next-generation multi-die systems. She graduated from University of Southern California with a Master's degree in Electrical Engineering and worked as a CAD engineer on the physical design and verification of block level IPs and SOCs, before making a transition to 3DIC Design Methodology.

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