Memory Technology Symposium 2022

Semiconductor chips and software have been the most uplifting phenomena in the history of humankind. The innovation model for chips and software is undergoing a major shift. The monolithic system-on-a-chip is being replaced by highly complex systems of chips. Antonio Varas discusses these trends and the challenges that must be overcome from both a technical and human productivity point of view. A new design paradigm is needed to keep innovation vibrant.

The Flat Field Transistor (FFT) has been developed as a low power alternative to the conventional 28nm and 22nm Bulk CMOS technology transistors for IoT and AI applications. Due to greatly improved electrostatic integrity and tolerance to low channel doping it offers up to 20% drive current increase and 50% reduction of threshold voltage mismatch complemented by approximately 5% reduction of manufacturing costs. In this talk we present a DTCO study of the application of the FFT in DRAM.

Although the DRAM cell transistors have undergone a dramatic revolution from recess gate to saddle FinFET, for cost reasons, the DRAM sense amplifiers and periphery continue to be manufactured using conventional bulk MOSFETs.

However, with the relentless scaling of the DRAM cell the margins of the sense amplifier (SA) dramatically decrease. The statistical variability (mismatch) of the bulk MOSFETs is the main factor eroding the SA margins. The addition of offset compensation circuits to the SA, adopted by most of the DRAM manufacturers, increases the SA related ‘dark’ area on the DRAM chips, further eroding the DRAM scaling.

The low statistical variability of the FFT makes it ideal candidate for DRAM sense amplifier applications. The advantages of the FFT in DRAM can be sustained down to 22nm bulk CMOS offering long-term DRAM scaling solution. The DTCO analysis shows that at 22nm bulk CMOS, the FFT delivers more than 50% reduction in the SA offset variability. This can be translated to more than 4 time reduction in the FFT SA area compared to the bulk MOSFET SA at identical offset variability distributions. The increased performance and reduced manufacturing cost of the FFT also favors its application in the rest of the DRAM periphery.

As DRAM products with higher capacity and higher speed are required, timing margins have become insufficient. As a result, performance degradation due to the deterioration of the power supply has become conspicuous, necessitating the need for PDN analysis. However, full chip simulation with PDN incurs significant performance degradation compared to normal post-layout full-chip simulation.

In this presentation, we would like to introduce various techniques that have helped us reduce the runtime of PDN Simulation through PrimeSim Pro and make full chip simulation with PDN practical.

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.  Compared to dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. STA is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a set of test vectors.   STA has traditionally been utilized at the logic block and chip level but is typically not used to develop timing rules for designs that contain custom or analog circuitry, such as embedded memories.  This talk will review some recent enhancements to and benefits of the NanoTime transistor-level static timing to verify the high-density and high-performance family of DesignWare embedded memory compilers from Synopsys.

SiMa.ai has the First purpose-built MLSoC™ platform with a software centric approach providing effortless machine learning (ML) deployment for the embedded edge ML market.The SiMa.ai MLSoC delivers high-performance, effortless machine learning for embedded edge applications. Built on 16nm technology, the MLSoC’s processing system consists of computer vision processors for image pre and post processing, coupled with dedicated machine learning acceleration and high-performance application processors. Surrounding the real-time intelligent video processing are memory interfaces, communication interfaces, and system management all connected via a network on chip (NoC).

The MLSoC features low operating power and high ML processing capacity, making it ideal as a standalone edge-based system controller or to add a machine learning offload accelerator for processors, ASICs and other devices.

One of the key features supported by the MLSoC chip are the interfaces to external LPDDR4 memory for storing application code, ML collaterals such as weights, images and compiled code among other things. 

Memories are critical building blocks for today’s SoCs and occupy 60-70% of the silicon area. With the rise in Automotive and AI applications, memory architectures are also evolving, to perform faster computations closer to the CPU, for example. Many of these chips being life-critical, safety has become an integral part of today’s memory designs, adding many extensive verification steps to deliver a robust design that meets the mission profile of the chip. In this talk, we would discuss some of these verification methodologies we use in STMicroelectronics to deliver a robust memory IP that caters to our automotive customers.

Recent advances in automotive SOCs, artificial intelligence accelerators and high-performance computing in data centers have led to an explosion in the adoption of emerging memories, from on-chip SRAMs; to specialty memories: CAMs & MRAMs; to off-chip DDR and HBM memories in chiplets/3DIC. This presentation will address today’s trends and discuss the reliability challenges of these emerging memories throughout their different lifecycle stages. It will focus on optimizing the health of such emerging memories by managing their silicon lifecycle stages: from silicon debug in early bring up; to self-test and repair during volume production stage to improve quality and yield; to power-on self-test in the field to address aging challenges; to periodic in-system checking to improve functional safety; and finally to fault tolerance and error correction during real-time mission mode. These SLM optimizations are realized by using on-chip IP and/or off-chip data analytics.

Moderated by: Anand Thiruvengadam, Segment Management Director

The demand for larger, faster, and more energy-efficient memory chips coupled with the need for bespoke solutions to cater to the needs of diverse applications such as high-performance computing (HPC), artificial intelligence (AI), 5G, and automotive is necessitating the need for new design and development paradigms such as design-technology co-optimization, design shift left and digitization, design reuse, heterogenous design and integration, design-for-reliability, and silicon lifecycle management. In this panel discussion, we will explore some of these paradigms with executives from industry leaders.