Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Verifying ARM AMBA 5 CHI Interconnect-Based SoCs Using Next-Generation VIP
Tushar Mattu, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Introduction
To meet the low-power, performance and functionality demands of advanced electronics products, virtually every SoC designed today is a multicore SoC. In this environment, on-chip cache memory plays a critical role, as memory architecture is fundamental in determining system performance.
Historically, CPU speed has outpaced memory speed. This performance gap led to the use of on-chip cache memory in single-processor systems to prevent the CPU from having to wait for instructions and data from memory. However, in a multicore SoC, individual cores must access and share data across the entire chip.
While cache control protocols were once implemented as flexible software implementations, the performance requirements of multi-block multi-threaded ICs have moved these into on-chip hardware implementations.
To address the issue of maintaining cache coherency in today's multicore chips, ARM® created the ARM® AMBA® ACE™ (AXI Coherency Extensions) and a number of interconnect implementations that use AXI4™ and ACE to deploy hardware-based cache coherency. Building on the ACE specification, ARM more recently released AMBA 5 CHI (coherent hub interface), a packet-based protocol developed to provide high-performance, cache-coherent communication between ARM Cortex®-A50 series processors. It is used with other ARM AMBA protocols to create cache-coherent SoC interconnects that encompass memory subsystems, signal processing, graphics processing and off-chip communication.
The AMBA 5 CHI enables users to ensure cache-coherent interconnects, yet there are always challenges in verifying a SoC through its various stages of design from interconnect, to RTL integration, to full SoC verification. Verification IP is a key element in meeting those challenges; however, the current generation of verification IP (VIP) is running out of steam to provide the performance, productivity and features to verify the design as RTL is incrementally integrated into the system.
Fortunately, next-generation SystemVerilog™ VIP enables the rapid creation of a multi-protocol verification environment for an AMBA-based SoC including CHI, ACE-Lite™ and other AMBA interfaces. It offers stimulus, system-wide data integrity checking, performance analysis, performance checking, protocol-aware debug and coverage closure.
AMBA 5 CHI Overview
The AMBA 5 CHI protocol is geared to offer users high performance on cache management. Achieving this requires a different architecture and communication methodology from previous generation protocols like ACE or AXI4. As a result, the protocol also requires a new VIP architecture and infrastructure that can both support the complexity of the protocol and offer the necessary verification performance for today's advanced requirements.
Figure 1: Cache coherent network based on ARM CoreLink CCN-504 diagram
In addition, it's important to note that the CHI protocol is not used in isolation. The ARM CoreLink™ Cache Coherent Network (figure 1) contains multiple interfaces. In this example, the CHI interface is used from the interconnect to the Cortex-A57s and DMC-520 memory controllers. The rest of the interfaces are a mixture of ACE-Lite, AXI4, AHB™ and APB™. It is therefore very important to have consistent verification IP working in a highly configurable environment to be able to adapt to the evolving testbenches needed to verify the interconnects, subsystems, and SoC.
Verification Challenge of Cache-Coherent Interconnect
The need for cache coherency is inherent in today's chips. Because CPU speed has historically outpaced memory speed, on-chip cache memory is commonly used to prevent processors from having to wait for instructions and data from memory.
Yet in the multicore SoC, cores must access and share data across the entire chip. Cache memories fetch and store data in local caches to facilitate data sharing. Cache coherency is about getting the right data to the right place at the right time.
A CHI-based system can help ensure cache coherency quickly.
Figure 2: Cache coherent interconnect in action
For example, figure 2 shows an example of a cache coherent system performing a load operation from a shareable location. Requester1 first sends a 'ReadShared' request to the interconnect (Step 1). The interconnect then sees if it has the cache line (u:5). If interconnect has the cache line, then the interconnect returns the data from the cache.
However, if the interconnect didn't have the cache line, then the interconnect will send a ReadShared snoop transaction to Requester2 (Step 2), and initiate the READ request from memory (Step 3b). Requester2 responds back with the data to the interconnect (Step 3a). The interconnect then returns the data to Requester1 (step 4). At this point, the cache lines corresponding to variable u in both Requester 1 & 2 are in a shared state, and cache coherency has been achieved.
Verifying such a system can be quite complex. There can be multiple scenarios and corner cases involved. But there are five key areas that must be verified:
- The interconnect maintains coherency across all the caches in the system
- If all the cache lines for a given address are in clean state, the content in these clean cache lines matches the content in the memory
- The interconnect issues the right set of snoop transactions for the coherent transactions, as defined in the specification
- The data returned back to the coherent transaction is consistent with the data returned by the snoop transaction. That is, whether interconnect maintains the integrity of data between the snoop and coherent transactions
- The sequencing order when snoop and coherent transactions access the same cache line as the same time matches the specification
Verification IP for AMBA 5 CHI Interconnect
Verification IP is an essential part of building a verification environment for an AMBA-based interconnects which will typically be made up of many varieties of AMBA-based interfaces. It enables traffic generation across the full spectrum of the protocols, data integrity checking, functional coverage reporting and debug capabilities to rapidly verify interconnects and IP blocks. In addition, commercial VIP is developed by dedicated AMBA experts and proven across multiple designs to help ensure compliance to the ARM specifications.
Building a verification environment around the ARM CoreLink CCN-504 Network in figure 1 first requires the placement of VIP at each port to represent the traffic generation and response across the interconnect. It then includes a System Monitor that will interact with all other VIP to ensure cache coherency across the system, as in the example above. As RTL is brought into the design replacing the VIP components, the VIP for that component is switched to passive mode. It now monitors the port for correct protocol behavior and checks for data integrity across the system utilizing the system monitor. Using Synopsys Protocol Analyzer, the system can now automatically track performance metrics such as latency and bus utilization, and use an intuitive, graphical user interface to analyze performance data.
With multiple types of VIP running at the same time, designers need to build this environment with performance in mind and to include a high-performance system monitor.
Figure 3: Cache coherent network with Synopsys Discovery™ VIP
Addressing Common AMBA 5 CHI Challenges with VC VIP
Synopsys' latest Verification Compiler™ (VC) VIP offers multiple performance advantages that address common challenges around AMBA 5 CHI support.
The first challenge many users face is in building their verification environment to get to first test. Synopsys offers a configurable GUI, built-in test plans and a comprehensive set of configurable sequences to rapidly configure a verification environment to get to first test. In addition, a test suite for AMBA 5 CHI interconnects is available as part of the VIP, delivered in source-code SystemVerilog UVM, to provide users with a comprehensive basis for exhaustive verification coverage.
The second challenge is often in time-to-verify. Most commercial VIP is written in C, e, or OpenVera® and then bloated with wrapper code needed to run in the verification environment. However, the VC VIP for AMBA 5 CHI is written in native SystemVerilog that can run up to 3X faster than wrapper-based VIP.
A third challenge can be time-to-debug, particularly if a user is not completely familiar with the intricacies of the CHI protocol. Synopsys VIP offers protocol-aware debug, source code visibility and error diagnostics that ease this process.
Finally, VC VIP enables users with efficient verification measurement by offering built-in coverage, graphical integration with the prebuilt verification plan, and sequence collections.
VC VIP for the AMBA 5 CHI protocol contains all the functionality included in the CHI protocol, including requester agents, a CHI system monitor that performs cache coherency checks at the system level, the CHI interconnect VIP environment, and the CHI system env which encapsulates the environment.
This VIP is provided as a top level AMBA system env component that instantiates a configurable number of CHI/AXI/AHB/APB subsystem environments, which in turn can be configured further for a number of requester/completer agents and their type. A user would instantiate this component in the testbench, which then automatically provides the system configuration object to the top level system env, and then instantiates it at the subsystem level. This offers users a fast and easy mechanism to build a comprehensive verification environment with UVM that runs natively on any simulator.
Conclusion
Cache coherent interconnect is a must have for multicore SoCs, and will only become more important with future generations.
Using Synopsys VC VIP, teams using the ARM AMBA 5 protocol, including AMBA 5 CHI, can rapidly set up and use a high-performance verification environment that ensures cache consistency across multiple cluster SoCs.
Additional Resources: ARM TechCon Interview