Transitioning from USB 2.0 HSIC to USB 3.0 SSIC

USB 2.0 HSIC Advantages and Disadvantages

The USB Implementers Forum (USB-IF) decided to reduce USB power consumption by eliminating the USB 2.0 PHY along with the associated analog circuitry. Previously, a USB 2.0 signal was converted from digital to analog, transmitted over a wire, and converted back from analog to digital in the USB PHY on the other SoC. With the new Hi-Speed Inter-Chip (HSIC) standard created by the HSIC USB-IF Working Group, signals can stay digital, transmit to the PCB over standard FR4 traces, and be received at the destination. Eliminating the analog circuitry of the USB 2.0 PHY is the essence of the USB 2.0 HSIC PHY.

The USB 2.0 HSIC PHY is one-third the size of a standard USB 2.0 PHY and consumes less than one-third the power. Active power in an HSIC PHY cuts power in a pair of devices by 72%, so major application processors for smartphones and LTE/3G modems now use HSIC. HSIC has been successful, but is lacking in two areas. First, a single USB 2.0 host can support only an effective throughput of 320 Mbps. For example, if you had a USB 2.0 hard drive (externally) and an HSIC modem (internally) connected to the same USB 2.0 host, and the hard drive consumed the throughput, then either the HSIC modem would be starved for data, or the bandwidth would be split and file transfer speed will be reduced by 30-50%. USB 2.0 can’t meet the throughput requirements of these applications.

Improving Speed, Power and Area with USB 3.0 SSIC and MIPI M-PHY

Fortunately, the USB-IF introduced USB 3.0 in 2008. While bringing increased in speed and throughput with USB 3.0, the USB-IF replaced HSIC with the SuperSpeed Inter-Chip (SSIC) standard for on-PCB communication. Where HSIC supported only the USB 2.0 speeds up to 320 Mbps, SSIC supports USB 3.0 speeds of 1.25 Gbps. 

To promote rapid adoption of SSIC, the USB-IF aligned SSIC with the MIPI Alliance’s gigabit-speed, on-PCB, chip-to-chip PHY called the MIPI M-PHY. The M-PHY standard consumes lower power and offers greater flexibility than USB 3.0 PHYs. M-PHYs can come in three speeds called Gears. Gear1 operates at 1.25 or 1.45 Gbps, Gear2 at 2.5 to 2.9 Gbps, and Gear3 up to 5.8 Gbps. In addition, M-PHYs can have 1, 2, or 4 lanes. Each lane has x pins, so 2 lanes have 2x pins and 4 lanes have 4x pins. These lane configurations offer flexibility either to run in multiple parallel lanes at slower clock speeds to save power, or to run at faster speeds but consume fewer pins. Since many SoCs are pin and/or pad limited, designers often choose the faster Gear3 standard to save pins. A MIPI 1 lane PHY has 16 pins. A standard USB 3.0 PHY has at least 15 pins including USB 2.0 D+ and D-; USB 3.0 Tx+,Tx- Rx+, Rx-, power, and ground pins.

The MIPI Alliance and USB-IF worked together to standardize the interface between USB 3.0 controllers and MIPI M-PHYs. According to the standard, the USB 3.0 controller uses a standard PIPE interface, which is the same interface for the USB 3.0 path to a USB 3.0 PHY. While the PIPE interface is preserved, the system still needs an interface to a standard M-PHY. The M-PHY v2.0 specification defines the SSIC interface to the M-PHY as the Reference M-PHY Module Interface (RMMI). The logic bridge between the USB 3.0 controller and the M-PHY is called the PHY Adapter. While it sounds simple, the PHY Adaptor is complex as it must synthesize and operate with the controller and the PHY. It must support USB 3.0 power savings modes (U1, U2, U3, and U4) while supporting 1, 2, or 4 lanes and/or Gear1, 2, or 3 speeds.

Just as the HSIC PHY is smaller than a USB 2.0 PHY, the MIPI M-PHY is about 50% smaller than a USB 3.0 PHY. Eliminating the USB 3.0 PHY saves half of the area. In addition, a MIPI M-PHY consumes significantly less power, especially in Gear1, 1 lane operation. In this configuration, a MIPI M-PHY consumes only 20% of the power of a USB 3.0 PHY. For two devices connected on PCB, this 80% power reduction during active operation at the system level is significant for portable devices. Part of this power savings is due to the smaller PHY, and part is because the Gear1, 1 lane M-PHY data rate is only 1.25 or 1.45 Gbps. As a USB 3.0 PHY always operates at 5 Gbps, the M-PHY allows for the lower data rate and power savings.

In most designs in the near future, a smartphone/tablet application processor SoC with a fully integrated USB 3.0 controller and M-PHY will connect on the PCB to a modem or WiFi SoC. The WiFi SoC also has an M-PHY and USB 3.0 controller. A second USB 3.0 controller and USB 3.0 PHY may be used for external USB connections. On the applications processor, this may be an external port for connecting to a USB 3.0 flash drive. In addition, the single M-PHY can be multiplexed with other MIPI functions. In Figure 1, a single M-PHY is used with an LLI controller to allow the baseband of a wireless device to use the RAM for the applications processor. By multiplexing a single PHY with two digital controllers, designers save the area of an extra M-PHY, as long as only one digital controller is working at any one time.

The introduction of the HSIC specification enabled an on-PCB interface with 67% power savings over USB 2.0 PHY. SSIC brings 80% power savings using a MIPI M-PHY and SSIC, as compared to a USB 3.0 PHY. The SSIC standard improves power efficiency while reducing area and maintaining throughput and preserving SSIC software compatibility. This makes SSIC attractive to designers of smartphones, tablets, and the wireless products they connect to, as SSIC offers bandwidth and power advantages in these highly competitive markets.