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Using L1 Sub-States to Reduce Power Consumption in PCI Express-Based Devices
By Scott Knowlton, Sr. Product Marketing Manager, Synopsys, Inc.
In many of today’s mobile multimedia, laptop, computer, server, networking and storage applications, PCI Express® (PCIe) has evolved into the interconnect of choice. PCI Special Interest Group (PCI-SIG), the standards body for PCIe, accomplished this by continually evolving the specification at an incredible rate to improve performance, increase efficiency, and lower power consumption, thereby satisfying the divergent needs of these applications.
Over the last couple of years, PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management. The Latency Tolerance Reporting (LTR) mechanism has been added to the specification, which tells the host the latency tolerance a device has in response to an interrupt from the device. This allows the host to judiciously decide how long to wait before servicing the interrupt from the device in order to coordinate multiple devices and achieve the maximum power optimizations for the system. Another addition, Optimized Buffer Flush/Fill (OBFF), enables the host to provide system state information, via messages, to devices. Devices use this system state information to optimize system power consumption—allowing the Host CPU and memory sub-system to power down and stay in their low power states longer.
The latest ECN from PCI-SIG aims to reduce power consumption while a device is in the suspend state (also known as “standby”) in order to extend the battery life as well as meeting the energy consumption standards set out by governments worldwide. Pulling your tablet or laptop out of your bag during a long flight, only to find that it consumed all of the battery power while it was in standby mode, is one of a business traveler’s nightmares. This experience is a lesson in how non-optimized systems consume a surprising amount of power while in the standby state. PCI-SIG is addressing this situation, as well as meeting the requirements set forth by international regulatory agencies for green, zero-consumption idle power.
While the PCIe specification includes an L1 low-power state, it alone does not meet the thin and light form factor requirements for idle power. Consumers are demanding that these devices have 8 to 10 hours of use time and seemingly an infinite amount of standby time. Of course, this has to be done with minimum added costs during product development while maintaining backwards compatibility.
A PCIe link is a serial link that directly connects two components, such as a Host and a Device as shown in Figure 1. Ignoring the state of the Host or the Device for this discussion, the PCIe link is defined to save power when the controlling link state machine (LTSSM) is in the L1 state. However, the PCIe interface has both analog and digital circuits and the L1 state doesn’t turn off all the analog circuits in the PHY. The Receiver Electrical Idle detector and the transmit common-mode voltage driver continue drawing power. The result is that each lane of the link can consume 10 to 25mW per lane while in standby…quietly draining the device’s battery.
Figure 1: L1 sub-states ECN reduces the power consumed by the link
Designers using the current low-power states of the PCIe specification can utilize the L1 state to reduce power consumption. The traditional L1 state allows the reference clock to be disabled on entry to L1, which is controlled by a configuration bit written to by software. However, the PCIe link still consumes too much power due to leakage, the transmit common–mode voltage circuit, and the Receiver Electrical Idle detector circuitry. The result for the end product user is drained batteries and unmet governmental regulations. To avoid these issues, the PCIe link must reduce its link idle power to approximately 10% of the active power, or in the range of 10s of microwatts.
The PCI-SIG community has just approved an enhancement to the L1 state called L1 sub-states. L1 sub-states adds two “pseudo sub-states,” called L1.1 and L1.2, to the LTSSM, which can be used to turn off additional analog circuits in the PHY. L1.1 allows the common-mode voltage to be maintained, while L1.2 allows all high-speed circuits to be turned off. In order to use L1.2, L1 sub-states also require the LTR ECN to be supported by the PCIe interface. The logical view of the LTSSM with the new L1 sub-states is shown in Figure 2.
Figure 2: Relationship of logical L1.1 and L1.2 modes to L1 state specification
Designers need to be aware of a few challenges that implementing the new L1.1 and L1.2 lower power sub-states may present. For example, L1 sub-states may require additional pins if the reference clock generator is off-chip and redefines the CLKREQ# signal to be bidirectional to allow handshaking with the system reference clock controller. Not all form factors support CLKREQ# (which is only defined in the mini-CEM card specification)—form factors that do not have CLKREQ# defined will need to use an in-band mechanism when it becomes available. This L1 sub-state solution is an out-of-band solution since it doesn’t use the differential signals of the PCIe link and there are additional discussions in place to provide an in-band solution utilizing the existing differential signals. The implementation of L1 sub-states also requires some silicon modifications to gate the power of the PCIe analog circuits and logic while retaining the port state. Of course, any modifications to support L1 sub-states must still support the default L1 legacy operation and the new features are enabled via system firmware during the driver’s discovery process of the link capabilities.
Table 1 shows the low power solutions available with the existing L1 state compared to using L1 sub-states. It is expected that the power savings scale linearly for multi-lane links and implementing the L1 sub-states feature reduces power consumption at the increase of the L1 exit latency. Implementing L1 sub-states is key to reducing power consumption for mobile designs using PCI Express.
Table 1: Comparison of proposed solutions
L1 sub-states has just been approved as a formal ECN by PCI-SIG, but the benefits are so important that several companies have already utilized Synopsys’ DesignWare IP for PCI Express solutions to implement L1 sub-states into their chips and have it available in silicon.
DesignWare IP Solution for PCI Express
The Synopsys DesignWare® IP for PCI Express solution provides the port logic necessary to implement and verify high-performance designs using the PCIe interconnect standard. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed-signal PHY, and verification IP, all of which are compliant with the PCIe 1.1, 2.1 and the 3.0 specifications.
Additional Resources
- Learn more about Synopsys DesignWare IP for Cloud Computing and HPC
- Learn more about Synopsys IP Solutions for PCI Express (PCIe)